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參數(shù)資料
| 型號： | IDT72V36110L7-5BBI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 46/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 131KX36 7-5NS 144BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲容量： | 4.7M（131K x 36） |
| 數(shù)據(jù)速率： | 166MHz |
| 訪問時(shí)間： | 5ns |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BGA |
| 供應(yīng)商設(shè)備封裝： | 144-PBGA（13x13） |
| 包裝： | 托盤 |
| 其它名稱： | 72V36110L7-5BBI 800-2341 IDT72V36110L7-5BBI-ND |
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7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 43-47 and Figures 31-33.
PIN DESCRIPTION (PBGA PACKAGE ONLY)
Symbol
Name
I/O
Description
ASYR(1)
Asynchronous
I
A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
Read Port
will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.
ASYW(1)
Asynchronous
I
A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
WritePort
will select Asynchronous operation.
TCK(2)
JTAG Clock
I
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the
device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change
on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
TDI(2)
JTAG Test Data
I
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
Input
seriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegisterandBypassRegister.
An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO(2)
JTAG Test Data
O
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
Output
seriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,IDRegisterandBypass
Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
TMS(2)
JTAG Mode
I
TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthedevicethrough
its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST(2)
JTAG Reset
I
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller will automatically reset upon
power-up. If the JTAG function is not used then this signal should to be tied to GND.
PIN DESCRIPTION-CONTINUED (TQFP & PBGA PACKAGES)
SEN
Serial Enable
I
SENenablesserialloadingofprogrammableflagoffsets.
WCLK/
WriteClock/
I
If Synchronous operation of the write port has been selected, when enabled by
WEN, the rising edge of WCLK
WR
WriteStrobe
writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into the FIFO
on a rising edge in an Asynchronous manner, (
WEN should be tied to its active state). Asynchronous operation of
the WCLK/WR input is only available in the PBGA package.
WEN
WriteEnable
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
VCC
+3.3V Supply
I
These are VCC supply inputs and must be connected to the 3.3V supply rail.
Symbol
Name
I/O
Description
NOTE:
1. Inputs should not change state after Master Reset.
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