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參數(shù)資料
| 型號： | IDT72V295L10PFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 17/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SUPERSYNC 10NS 64-TQFP |
| 標準包裝： | 45 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲容量： | 2.3K（64 x 36） |
| 訪問時間： | 10ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-TQFP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1255 (CN2011-ZH PDF) |
| 其它名稱： | 72V295L10PFG 800-1528 |
24
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the
EF and FF functions in IDT Standard mode
and the
IR and OR functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for
EF/FF deassertion and IR/OR
assertion to vary by one cycle between FIFOs. In IDT Standard mode, such
Figure 19. Block Diagram of 131,072 x 36 and 262,144 x 36 Width Expansion
problems can be avoided by creating composite flags, that is, ANDing
EF
of every FIFO, and separately ANDing
FF of every FIFO. In FWFT mode,
composite flags can be created by ORing
ORof every FIFO, and separately
ORing
IR of every FIFO.
Figure 23 demonstrates a width expansion using two IDT72V295/
72V2105 devices. D0-D17 from each device form a 36-bit wide input bus
and Q0-Q17 from each device form a 36-bit wide output bus. Any word width
can be attained by adding additional IDT72V295/72V2105 devices.
WRITE CLOCK (WCLK)
m + n
mn
MASTER RESET (MRS)
READ CLOCK (RCLK)
DATA OUT
nm + n
WRITE ENABLE (WEN)
FULL FLAG/INPUT READY (FF/IR) #1
PROGRAMMABLE (PAF)
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
OUTPUT ENABLE (OE)
READ ENABLE (REN)
m
LOAD (LD)
IDT
72V295
72V2105
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PARTIAL RESET (PRS)
IDT
72V295
72V2105
4668 drw 22
FULL FLAG/INPUT READY (FF/IR) #2
HALF-FULL FLAG (HF)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
FIFO
#2
GATE
(1)
GATE
(1)
D0
- Dm
DATA IN
Dm+1 - Dn
Q0
- Qm
Qm+1 - Qn
FIFO
#1
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參數(shù)描述 |
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| IDT72V295L10PFG8 | 功能描述:IC FIFO SUPERSYNCII 10NS 64-TQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V295L15PF | 功能描述:IC FIFO SUPERSYNCII 15NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V295L15PF8 | 功能描述:IC FIFO SUPERSYNCII 15NS 64-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72V295L15PFGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SUPERSYNCII 15NS 64-TQFP |
| IDT72V295L15PFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SUPERSYNCII 15NS 64-TQFP |
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