SUPERSYNC FIFOTM
參數(shù)資料
型號(hào): IDT72V295L10PFG
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 11/26頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SUPERSYNC 10NS 64-TQFP
標(biāo)準(zhǔn)包裝: 45
系列: 72V
功能: 同步
存儲(chǔ)容量: 2.3K(64 x 36)
訪問(wèn)時(shí)間: 10ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 1255 (CN2011-ZH PDF)
其它名稱(chēng): 72V295L10PFG
800-1528
19
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
Figure
10.
Read
Timing
(First
Word
Fall
Through
Mode)
NOTES:
1.
t
SKEW1
is
the
minimum
time
between
a
rising
RCLK
edge
and
a
rising
WCLK
edge
to
guarantee
that
IR
will
go
LOW
after
one
WCLK
cycle
plus
t
WFF
.If
the
time
between
the
rising
edge
of
RCLK
and
the
rising
edge
of
WCLK
is
less
than
t
SKEW1
,
then
the
IR
assertion
may
be
delayed
one
extra
WCLK
cycle.
2.
tSKEW2
is
the
minimum
time
between
a
rising
RCLK
edge
and
a
rising
WCLK
edge
to
guarantee
that
PAF
will
go
HIGH
after
one
WCLK
cycle
plus
t
PAF
.
If
the
time
between
the
rising
edge
of
RCLK
and
the
rising
edge
of
WCLK
is
less
than
tSKEW2
,then
the
PAF
deassertion
may
be
delayed
one
extra
WCLK
cycle.
3.
LD
=
HIGH
4.
n=
PAE
Offset,
m
=
PAF
offset
and
D
=
maximum
FIFO
depth.
5.
D
=
131,073
for
IDT72V295
and
262,145
for
IDT72V2105.
WCLK
12
WEN
D
0
-
D
17
RCLK
tENS
REN
Q
0
-Q
17
PAF
HF
PAE
IR
OR
W
1
W
1
W
2
W
3
W
m+2
W
[m+3]
tOHZ
tSKEW1
(1)
tENH
tDS
tOE
tA
tPAF
tWFF
tENS
OE
tSKEW2
(2)
W
D
4668
drw
13
tPAE
W
[D-n]
W
[D-n-1]
tA
tHF
]
[
W
]
[
W
tREF
W
[D-1]
W
D
tA
W
[D-n+1]
W
[m+4]
W
[D-n+2]
tENS
1
tDH
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