IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
參數(shù)資料
型號(hào): IDT72V2113L6BC
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 29/46頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SUPERSYNCII 6NS 100-BGA
標(biāo)準(zhǔn)包裝: 1
系列: 72V
功能: 同步
存儲(chǔ)容量: 4.7Mb(262k x 18)
訪問(wèn)時(shí)間: 4ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LBGA
供應(yīng)商設(shè)備封裝: 100-CABGA(11x11)
包裝: 托盤
其它名稱: 72V2113L6BC
35
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
JUNE 1, 2010
NOTES:
1. n =
PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4.
PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9
Input and x9 Output bus Widths are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113.
2. In FWFT mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input
and x9 Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113.
Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
tENS
tENH
WEN
PAE
tENS
n + 1 words in FIFO(2),
n+2wordsinFIFO(3)
n words in FIFO(2),
n + 1 words in FIFO(3)
RCLK
tPAEA
REN
6119 drw24
n words in FIFO(2),
n + 1 words in FIFO(3)
tPAEA
tCLKL
tCLKH
Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
WCLK
tENS
tENH
WEN
HF
tENS
tHF
RCLK
tHF
REN
6119 drw25
tCLKL
tCLKH
D/2 words in FIFO(1),
[
] words in FIFO(2)
D + 1
2
[ + 1] words in FIFO(1),
[
] + 1 words in FIFO(2)
D + 1
2
D
2
D/2 words in FIFO(1),
[
] words in FIFO(2)
D + 1
2
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