SUPERSYNC FIFOTM
參數資料
型號: IDT72V2111L10PFG8
廠商: IDT, Integrated Device Technology Inc
文件頁數: 4/27頁
文件大?。?/td> 0K
描述: IC FIFO SS 512X9 10NS 64QFP
標準包裝: 750
系列: 72V
功能: 同步
存儲容量: 4.6K(512 x 9)
訪問時間: 10ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72V2111L10PFG8
12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9
When
EF goes HIGH, Retransmit setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard
mode is selected, every word read including the first word following
Retransmit setup requires a LOW on
RENtoenabletherisingedgeofRCLK.
SeeFigure11,RetransmitTiming(IDTStandardMode),fortherelevanttiming
diagram.
If FWFT mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting
OR HIGH. During this period, the internal read
pointer is set to the first location of the RAM array.
When
OR goes LOW, Retransmit setup is complete; at the same time,
the contents of the first location appear on the outputs. Since FWFT mode
isselected,thefirstwordappearsontheoutputs,noLOWon
RENisnecessary.
ReadingallsubsequentwordsrequiresaLOWon
RENtoenabletherisingedge
of RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant
timingdiagram.
For either IDT Standard mode or FWFT mode, updating of the
PAE, HF
and
PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
synchronized to RCLK, thus on the second rising edge of RCLK after
RT is
setup, the
PAE flag will be updated. HF is asynchronous, thus the rising
edge of RCLK that
RT is setup will update HF. PAF is synchronized to
WCLK, thus the second rising edge of WCLK that occurs tSKEW after the
rising edge of RCLK that
RT is setup will update PAF. RT is synchronized
to RCLK.
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