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參數(shù)資料
| 型號： | IDT72T7295L10BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 24/53頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 32768X72 10NS 324-BGA |
| 標準包裝： | 1 |
| 系列： | 72T |
| 訪問時間： | 10ns |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-BGA |
| 供應(yīng)商設(shè)備封裝： | 324-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T7295L10BB |
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30
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
Figure 8. TAP Controller State Diagram
Test-Logic
Reset
Run-Test/
Idle
1
0
Select-
DR-Scan
Select-
IR-Scan
1
Capture-IR
0
Capture-DR
0
EXit1-DR
1
Pause-DR
0
Exit2-DR
1
Update-DR
1
Exit1-IR
1
Exit2-IR
1
Update-IR
1
0
1
5994 drw13
0
Shift-DR
0
Shift-IR
0
Pause-IR
0
1
Input = TMS
0
1
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1) for the full state diagram
All state transitions within the TAP controller occur at the rising edge of the
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the FIFO memory and must be reset after power up of the device. See
TRST description for more details on TAP controller reset.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenablingthe
normaloperationoftheIC.TheTAPcontrollerstatemachineisdesignedinsuch
awaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-Logic-Reset
state can be entered by holding TMS at high and pulsing TCK five times. This
is the reason why the Test Reset (
TRST) pin is optional.
Run-Test-Idle In this controller state, the test logic in the IC is active only if
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
test, then it will be executed when the controller enters this state. The test logic
in the IC is idles otherwise.
Select-DR-Scan This is a controller state where the decision to enter the
Data Path or the Select-IR-Scan state is made.
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate
other wise.
Capture-IR In this controller state, the shift register bank in the Instruction
Register parallel loads a pattern of fixed values on the rising edge of TCK. The
last two significant bits are always required to be “01”.
Shift-IR In this controller state, the instruction register gets connected
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction
register.
Exit1-IR ThisisacontrollerstatewhereadecisiontoentereitherthePause-
IR state or Update-IR state is made.
Pause-IR This state is provided in order to allow the shifting of instruction
register to be temporarily halted.
Exit2-DR This is a controller state where a decision to enter either the Shift-
IR state or Update-IR state is made.
Update-IR In this controller state, the instruction in the instruction register is
latched in to the latch bank of the Instruction Register on every falling edge of
TCK. This instruction also becomes the current instruction once it is latched.
Capture-DR In this controller state, the data is parallel loaded in to the data
registers selected by the current instruction on the rising edge of TCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and
Update-IR states in the Instruction path.
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by
TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
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