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參數(shù)資料
| 型號： | IDT723653L15PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 23/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 2048X36 128-TQFP |
| 產(chǎn)品變化通告： | Product Discontinuation 27/Jul/2009 |
| 標準包裝： | 1,000 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 72K（2K x 36） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問時間： | 15ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應商設備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 723653L15PF8 |
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COMMERCIALTEMPERATURERANGE
IDT723653/723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
Communication between each port may bypass the FIFO via two mailbox
registers. The mailbox registers' width matches the selected Port B bus width.
Each mailbox register has a flag (
MBF1 and MBF2) to signal when new mail
has been stored.
Two kinds of reset are available on these FIFOs: Reset and Partial Reset.
Resetinitializesthereadandwritepointerstothefirstlocationofthememoryarray
and selects serial flag programming, parallel flag programming, or one of five
possible default flag offset settings, 8, 16, 64, 256 or 1,024.
Partial Reset also sets the read and write pointers to the first location of the
memory. Unlike Reset, any settings existing prior to Partial Reset (i.e.,
programmingmethodandpartialflagdefaultoffsets)areretained.PartialReset
is useful since it permits flushing of the FIFO memory without changing any
configurationsettings.
TheFIFOhasRetransmitcapability,aRetransmitisperformedafterfourclock
cycles of CLKA and CLKB, by taking the Retransmit pin,
RT LOW while the
Retransmit Mode pin,
RTMisHIGH.WhenaRetransmitisperformedtheread
pointer is reset to the first memory location.
These devices have two modes of operation: In theIDT Standard mode, the
first word written to an empty FIFO is deposited into the memory array. A read
operation is required to access that word (along with all other words residing
in memory). In theFirst Word Fall Through mode(FWFT), the first word written
to an empty FIFO appears automatically on the outputs, no read operation
required (Nevertheless, accessing subsequent words does necessitate a
formal read request). The state of the BE/
FWFT pinduringResetdetermines
the mode in use.
The FIFO has a combined Empty/Output Ready Flag (
EF/OR ) and a
combinedFull/InputReadyFlag(
FF/IR).TheEFandFFfunctionsareselected
in the IDT Standard mode.
EF indicates whether or not the FIFO memory is
empty.
FF shows whether the memory is full or not. The IR and OR functions
are selected in the First Word Fall Through mode. IR indicates whether or not
theFIFOhasavailablememorylocations.ORshowswhethertheFIFOhasdata
available for reading or not. It marks the presence of valid data on the outputs.
TheFIFOhasaprogrammableAlmost-Emptyflag(
AE)andaprogrammable
Almost-Full flag (
AF). AE indicates when a selected number of words remain
intheFIFOmemory.
AFindicateswhentheFIFOcontainsmorethanaselected
number of words.
FF/IR andAF are two-stage synchronized to the port clock that writes data
into its array.
EF/ORandAEaretwo-stagesynchronizedtotheportclockthat
reads data from its array. Programmable offsets for
AE and AF are loaded in
parallel using Port A or in serial via the SD input. Five default offset settings are
also provided. The
AEthresholdcanbesetat8,16,64,256or1,024locations
from the empty boundary and the
AF threshold can be set at 8, 16, 64, 256 or
1,024locationsfromthefullboundary.AllthesechoicesaremadeusingtheFS0,
FS1 and FS2 inputs during Reset.
Interspersed Parity is available and can be selected during a Master Reset
oftheFIFO.IfInterspersedParityisselectedthenduringparallelprogramming
of the flag offset values, the device will ignore data line A8 . If Non-Interspersed
Parity is selected then data line A8 will become a valid bit.
Two or more devices may be used in parallel to create wider data paths. In
First Word Fall Through mode, more than one device may be connected in
series to create greater word depths. The addition of external components is
unnecessary.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the Power Down state.
The IDT723653/723663/723673 are characterized for operation from 0
°C
to 70
°C.Industrialtemperaturerange(-40°Cto+85°C)isavailablebyspecial
order. They are fabricated using IDT’s high speed, submicron CMOS technol-
ogy.
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT723654L12PF | 功能描述:IC FIFO BI SYNC 4096X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723654L12PF8 | 功能描述:IC FIFO BI SYNC 4096X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723654L15PF | 功能描述:IC FIFO BI SYNC 4096X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723654L15PF8 | 功能描述:IC FIFO BI SYNC 4096X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723656L12PF | 功能描述:IC FIFO SYNC 4096X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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