參數(shù)資料
型號(hào): IDT723642L15PF8
廠(chǎng)商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 23/25頁(yè)
文件大小: 0K
描述: IC FIFO SYNC 2048X36 120QFP
標(biāo)準(zhǔn)包裝: 750
系列: 7200
功能: 同步
存儲(chǔ)容量: 72K(2K x 36)
數(shù)據(jù)速率: 67MHz
訪(fǎng)問(wèn)時(shí)間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 120-LQFP
供應(yīng)商設(shè)備封裝: 120-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱(chēng): 723642L15PF8
7
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723622/723632/723642 with CLKA
and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x [ICC(f) + (N x
ICC x dc)] + Σ(CL x VCC2 X fo)
where:
N
=
number of outputs = 36
ICC
=
increase in power supply current for each input at a TTL HIGH level
dc
=
duty cycle of inputs at a TTL HIGH level of 3.4 V
CL
=
outputcapacitanceload
fo
=
switching frequency of an output
Figure 1. Typical Characteristics: Supply Current (ICC) vs Clock Frequency (fS)
010
20
30
40
50
60
70
0
50
100
250
300
VCC = 5.0V
fS
Clock Frequency MHz
fdata = 1/2 fS
TA = 25
°C
CL = 0pF
VCC = 5.5V
3022 drw 03a
200
150
VCC = 4.5V
80
90
ICC(f)
Supply
Current
mA
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