參數(shù)資料
型號: IDT723626L12PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/35頁
文件大?。?/td> 0K
描述: IC FIFO SYNC 256X36X2 128QFP
標準包裝: 1,000
系列: 7200
功能: 同步
存儲容量: 18.4K(256 x 36 x 2)
數(shù)據(jù)速率: 83MHz
訪問時間: 12ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應商設備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 723626L12PF8
1
FEBRUARY 2009
IDT723626
IDT723636
IDT723646
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3271/5
CMOS TRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2
1,024 x 36 x 2
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIALTEMPERATURERANGE
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
Memory storage capacity:
IDT723626 – 256 x 36 x 2
IDT723636 – 512 x 36 x 2
IDT723646 – 1,024 x 36 x 2
Clock frequencies up to 83 MHz (8ns access time)
Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
Select IDT Standard timing (using EFA, EFB, FFA, and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags
Big- or Little-Endian format for word and byte bus sizes
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
Green parts available, see ordering information
DESCRIPTION:
TheIDT723626/723636/723646isamonolithic,high-speed,low-power,
CMOS Triple Bus synchronous (clocked) FIFO memory which supports clock
Mail 1
Register
Programmable Flag
Offset Registers
Input
Register
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
Input
Register
Output
Register
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
MRS1
Mail 2
Register
MBF2
WENC
Port-C
Control
Logic
FIFO2,
Mail2
Reset
Logic
MRS2
MBF1
FIFO1
FIFO2
10
EFB/ORB
AEB
18
FFC/IRC
AFC
B0-B17
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A0-A35
EFA/ORA
AEA
3271 drw01
36
Output
Bus-
Matching
Output
Register
PRS2
PRS1
Timing
Mode
FWFT
C0-C17
CLKB
Port-B
Control
Logic
Common
Port
Control
Logic
(B and C)
BE
SIZEB
SIZEC
CLKC
MBC
36
Input
Bus-
Matching
RENB
MBB
CSB
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