參數(shù)資料
型號: IDT723616L15PF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 15/26頁
文件大小: 0K
描述: IC FIFO TRPL BUS 64X36X2 128QFP
標準包裝: 72
系列: 7200
功能: 同步
存儲容量: 4.6K(64 x 36 x2)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應商設備封裝: 128-TQFP(14x20)
包裝: 托盤
其它名稱: 723616L15PF
22
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723616 CMOS TRIPLE BUS SyncFIFO
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for
FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB
edge and rising CLKA edge is less than tSKEW1, then
FFA may transition HIGH one CLKA cycle later than shown.
2. Port-B size is word or byte; tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively. (The word-size case is shown.)
Figure 14.
FFA
FFA Flag Timing and First Available Write when FIFO1 is Full
EFB
RENB
B0 - B17
CLKB
FFA
CLKA
CSA
3520 drw14
WRA
12
A0 - A35
ENA
tCLK
tCLKH
tCLKL
tA
tSKEW1
tCLK
tCLKH
tCLKL
tENS
tDS
tENH
tDH
To FIFO1
Read 2
HIGH
LOW
HIGH
(1)
FIFO1 Full
tWFF
Read 1
tA
tEN
Previous Word in
FIFO1 Output Register
tENH
tDIS
tENS
Figure 13.
EFA
EFA Flag Timing and First Data Read when FIFO2 is Empty
FFC
C0 - C17
CLKA
EFA
CSA
W/RA
WENC
ENA
A0 -A35
CLKC
12
3520 drw13
tCLKH
tCLKL
tCLK
tENS
tENH
tDS
tDH
tSKEW1
tCLK
tCLKL
tENS
tENH
tA
W1
FIFO2 Empty
LOW
tCLKH
HIGH
(1)
tREF
tDS
tDH
Write 1
Write 2
NOTES:
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for
EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC
edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
2. Port-C size is word or byte; tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively. (The word-size case is shown.)
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