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參數(shù)資料
| 型號： | IDT72125L50SO8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 1KX16 PAR-SER 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 7200 |
| 功能： | 異步 |
| 存儲容量： | 16K (1K x 16) |
| 訪問時間： | 50ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.345"，8.77mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72125L50SO8 |
2
INDUSTRIAL TEMPERATURE RANGE
IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
PIN CONFIGURATION
PIN DESCRIPTIONS
PLASTIC THIN DIP (P28-2, order code: TP)
SOIC (SO28-3, order code: SO)
TOP VIEW
5
6
7
8
9
10
11
12
13
D2
D3
D4
GND
1
2
3
4
14
28
27
26
25
24
23
22
21
RSOX/
/DIR
Vcc
SO
SOCP
20
19
18
17
16
15
D1
D0
D13
D14
D15
D12
RSIX
D5
D6
D7
D9
D10
D11
D8
2665 drw 02
Symbol
Name
I/O
Description
D0–D15
Inputs
I
Data inputs for 16-bit wide data.
RS
Reset
I
When
RS is set low, internal READ and WRITE pointers are set to the first location of the RAM
array.
FF and HF go HIGH. EF and AEF go LOW. A reset is required before an initial WRITE
after power-up.
W must be high during the RS cycle. Also the First Load pin (FL) is programmed
only during Reset.
W
Write
I
A write cycle is initiated on the falling edge of WRITE if the Full Flag (
FF) is not set. Data set-up
and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored in the
RAM array sequentially and independently of any ongoing read operation.
SOCP
Serial Output
Clock
I
A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (
EF) is not set. In
both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together.
FL/DIR
First Load/
Direction
I
This is a dual purpose input used in the width and depth expansion configurations. The First
Load (
FL) function is programmed only during Reset (RS) and a LOW on FL indicates the first
device to be loaded with a byte of data. All other devices should be programmed HIGH. The
Direction (DIR) pin controls shift direction after Reset and tells the device whether to read out the
Least Significant or Most Significant bit first.
RSIX
Read Serial In
Expansion
I
In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain
expansion, RSIX is connected to RSOX (expansion out) of the previous device.
SO
Serial Output
O
Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending
on the Direction pin programming. During Expansion the SO pins are tied together.
FF
Full Flag
O
When
FF goes LOW, the device is full and further WRITE operations are inhibited. When FF is
HIGH, the device is not full.
EF
Empty Flag
O
When
EF goes LOW, the device is empty and further READ operations are inhibited. When EF is
HIGH, the device is not empty.
HF
Half-Full Flag
O
When
HF is LOW, the device is more than half-full. When HF is HIGH, the device is empty to
half-full.
RSOX/
AEF Read Serial
Out Expansion
Almost-Empty,
Almost-Full
Flag
O
This is a dual purpose output. In the single device configuration (RSIX HIGH), this is an
AEF
output pin. When
AEF is LOW, the device is empty-to-(1/8 full -1) or (7/8 full +1)-to-full. When
AEF is HIGH, the device is 1/8-full up to 7/8-full. In the Expansion configuration (RSOX
connected to RSIX of the next device) a pulse is sent from RSOX to RSIX to coordinate the
width, depth or daisy chain expansion.
VCC
Power Supply
Single power supply of 5V.
GND
Ground
Single ground of 0V.
2665 tbl 01
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| IDT72125L50TP | 功能描述:IC FIFO 1KX16 PAR-SER 28DIP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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