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參數(shù)資料
| 型號： | IDT70125S55JGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| 中文描述： | 高速2K × 9雙端口靜態(tài)RAM繁忙 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 139K |
| 代理商： | IDT70125S55JGI |
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
Timing Waveform of
BUSY
Arbritration Controlled by Address
(1)
t
RC
OR t
WC
APRIL 05, 2006
AC Elec tric al Charac teristic s Over the
Operating Temperature and S upply Voltage Range
(1)
NOTES
:
1. 'X' in part numbers indicates power rating (S or L).
t
BAA
ADDR
'A'
BUSY
'B'
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
t
APS
(2)
t
BDA
ADDR
'B'
2654 drw 12
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Mn.
Max.
Unit
INTERRUPT TIMING
t
AS
Address Set-up Time
0
____
0
____
ns
t
WR
Write Recovery Time
0
____
0
____
ns
t
INS
Interrupt Set Time
____
25
____
35
ns
t
INR
Interrupt Reset Time
____
25
____
35
ns
2654 tbl 12a
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
Symbol
Parameter
Min.
Max.
Mn.
Max.
Unit
INTERRUPT TIMING
t
AS
Address Set-up Time
0
____
0
____
ns
t
WR
Write Recovery Time
0
____
0
____
ns
t
INS
Interrupt Set Time
____
40
____
45
ns
t
INR
Interrupt Reset Time
____
40
____
45
ns
2654 tbl 12b
NOTES:
1. All timng is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite fromport “A”.
2. If
t
APS
is not satisified, the
BUSY
will be asserted on one side or the other, but there is no guarantee on which side
BUSY
will be asserted
(70121 only).
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