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參數(shù)資料
| 型號： | IDT70125S55JGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| 中文描述： | 高速2K × 9雙端口靜態(tài)RAM繁忙 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大小： | 139K |
| 代理商： | IDT70125S55JGI |
11
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
T iming Waveform of Write with Port-to-Port Read and
BUSY
(1,2,3)
APRIL 05, 2006
t
APS
ADDR
'A'
DATA
IN'A'
MATCH
t
WC
t
WP
R/
W
'A'
ADDR
'B'
DATA
OUT 'B'
MATCH
BUSY
'B'
t
BDA
t
DW
t
DH
VALID
VALID
t
DDD
(4)
t
WDD
t
BDD
2654 drw 09
(1)
Timing Waveform of
BUSY
Arbritration Controlled by
CE
T iming
(1)
T iming Waveform of Write with
BUSY
(3)
NOTES:
1. t
WH
must be met for both
BUSY
input (slave) and output (master).
2.
BUSY
is asserted on port 'B' blocking R/
W
'B',
until
BUSY
'B'
goes HIGH.
3. All timng is the same for left and right ports. Port"A" may be either left or right port. Port "B" is the opposite fromport "A".
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS
is ignored for Slave (IDT70125).
2.
CE
L
=
CE
R
= V
IL
3.
OE
= V
IL
for the reading port.
4. All timng is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is oppsite fromport "A".
2654 drw 10
R/
W
"A"
BUSY
"B"
t
WP
t
WB
R/
W
"B"
t
WH
(1)
(2)
t
BDC
ADDR
"A
and
B"
BUSY
"B"
CE
"A"
t
APS
(2)
t
BAC
ADDRESSES MATCH
CE
"B"
2654 drw 11
(1)
NOTES:
1. All timng is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite fromport “A”.
2. If t
APS
is not satisified, the
BUSY
will be asserted on one side or the other, but there is no guarantee on which side
BUSY
will be asserted
(70121 only).
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