參數(shù)資料
型號: IDT70121S
廠商: Integrated Device Technology, Inc.
英文描述: Low-Power JFET-Input Operational Amplifier 8-SOIC 0 to 70
中文描述: 高速2K × 9雙端口靜態(tài)RAM繁忙
文件頁數(shù): 5/12頁
文件大小: 168K
代理商: IDT70121S
6.10
5
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE
(1,2,4)
ADDRESS
DATA
OUT
t
RC
t
OH
PREVIOUS DATA VALID
t
AA
t
OH
DATA VALID
2654 drw 05
t
BDD
(3,4)
BUSY
OUT
NOTES:
1. Timing depends on which signal is aserted last,
OE
or
CE
.
2. Timing depends on which signal is deaserted first,
OE
or
CE
.
3. t
BDD
delay is required only in a case where the opposite port is completing
a write operation to the same address location. For simultanious read operations
BUSY
has no relationship to valid output data.
4. Start of valid data depends on which timing becomes effective last, t
AOE
,
t
ACE
,
t
AA
, or
t
BDD
.
5. R/
W
= V
IH,
and the address is valid prior to other coincidental with
CE
transition Low.
6. R/
W
= V
IH,
CE
= V
IL, and
OE
= V
IL.
Address is valid prior to or coincident with
CE
transition Low.
CE
t
ACE
t
AOE
t
HZ
t
LZ
t
PD
VALID DATA
t
PU
50%
OE
DATA
OUT
CURRENT
I
CC
I
SS
50%
2654 drw 06
(4)
t
LZ
t
HZ
(1)
(1)
(4)
(2)
(2)
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE
(5,6)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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