參數(shù)資料
型號(hào): IDT70121S45J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
中文描述: 2K X 9 DUAL-PORT SRAM, 45 ns, PQCC52
封裝: 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52
文件頁數(shù): 2/12頁
文件大小: 168K
代理商: IDT70121S45J
6.10
2
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (Cont'd):
Fabricated using IDT’s CMOS high-performance
technology, these devices typically operate on only 500mW of
power. Low-power (L) versions offer battery backup data
PIN CONFIGURATIONS
(1,2)
RECOMMENDED OPERATING TEMPERATURE
AND SUPPLY VOLTAGE
Grade
Commercial
Ambient Temperature
0
°
C to +70
°
C
GND
0V
V
CC
5.0V
±
10%
2654 tbl 02
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5
0
Max.
5.5
0.0
6.0
(2)
0.8
Unit
V
V
V
V
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.5V.
2654 tbl 03
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
Rating
Commercial
–0.5 to +7.0
Unit
V
Terminal Voltage
with Respect to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
T
A
0 to +70
°
C
T
BIAS
–55 to +125
°
C
T
STG
–55 to +125
°
C
I
OUT
50
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
2. V
TERM
must not exceed Vcc + 0.5V for more than 25% of the cycle time or
10ns maximum, and is limited to < 20mA for the period of V
TERM
> V
cc
+
0.5V.
2654 tbl 01
retention capability with each port typically consuming 200
μ
W
from a 2V battery.
The IDT70121/IDT70125 devices are packaged in a 52-pin
PLCC.
CAPACITANCE
(1)
(T
A
= +25
°
C, f = 1.0MHz)
Symbol
Parameter
C
IN
Input Capacitance
C
OUT
Output Capacitance
NOTES:
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
Condition
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
2654 tbl 13
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate the orientation of the actual part-marking.
A
9R
I/O
8R
I/O
7R
G
2
2
2
2
2
2
2
2
2
3
3
3
7
6
5
4
3
2
5
5
5
4
4
4
3
8
9
10
11
12
13
14
15
16
17
18
19
20
IDT70121/125
J52-1
A
6L
A
7L
A
8L
A
9L
A
1L
A
2L
A
3L
A
4L
A
5L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
46
45
44
43
42
41
40
39
38
37
36
35
34
A
5R
A
6R
A
7R
A
8R
A
0R
A
1R
A
2R
A
3R
A
4R
1
INDEX
OE
R
2654 drw 02
PLCC
TOP VIEW
(3)
A
1
I
R
R
W
R
C
R
V
C
C
L
I
L
A
1
O
L
A
0
I
4
I
5
I
6
I
7
I
8
I
0
I
1
I
2
I
3
I
4
I
5
I
6
B
R
R
W
L
B
L
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