參數(shù)資料
型號: IDT6198S55DB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: Dual Low-Power JFET-Input General-Purpose Operational Amplifier 8-TSSOP -40 to 85
中文描述: 16K X 4 STANDARD SRAM, 55 ns, CDIP24
封裝: 0.300 INCH, CERDIP-24
文件頁數(shù): 6/8頁
文件大?。?/td> 79K
代理商: IDT6198S55DB
6.3
6
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2
(1, 2, 4)
ADDRESS
DATA
OUT
2987 drw 08
t
RC
t
AA
t
OH
t
OH
DATA VALID
PREVIOUS DATA VALID
TIMING WAVEFORM OF READ CYCLE NO. 3
(1, 3, 4)
DATA
OUT
CS
I
CC
I
SB
V
CC
SUPPLY
CURRENT
2987 drw 09
t
ACS
(5)
t
CLZ
t
CHZ
t
PD
t
PU
(5)
DATA VALID
NOTES:
1.
WE
is HIGH for Read cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address valid prior to or coincident with
CS
transition LOW.
4.
OE
is LOW.
5. Transition is measured
±
200mV from steady state voltage.
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, All Temperature Ranges)
6198S15
(1)
6198L15
(1)
6198S20
6198L20
6198S25
6198L25
6198S35
6198L35
6198S45/55
(2)
6198S70/85
(2)
6198L45/55
(2)
6198L70/85
(2)
Symbol
Parameter
Min.
Max. Min. Max. Min.
Max. Min. Max.
Min. Max. Min. Max. Unit
Write Cycle
t
WC
Write Cycle Time
14
17
20
30
40/50
60/75
ns
t
CW
Chip Select to End-of-Write
14
17
20
25
35/50
60/75
ns
t
AW
Address Valid to End-of-Write
14
17
20
25
35/50
60/75
ns
t
AS
Address Set-up Time
0
0
0
0
0
0
ns
t
WP
Write Pulse Width
14
17
20
25
35/50
60/75
ns
t
WR
t
WHZ(3)
Write Recovery Time
0
0
0
0
0
0
ns
Write Enable to Output in High-Z
5
6
7
10
15/25
30/40
ns
t
DW
Data Valid to End-of-Write
10
10
13
15
20/25
30/35
ns
t
DH
t
OW(3)
Data Hold Time
0
0
0
0
0
0
ns
Output Active from End-of-Write
5
5
5
5
5
5
ns
NOTES:
1. 0
°
to +70
°
C temperature range only.
2. –55
°
C to +125
°
C temperature range only.
3. This parameter is guaranteed by device characterization, but is not production tested.
2987 tbl 12
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