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參數(shù)資料
| 型號： | IDT5V995PFGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK |
| 中文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP44 |
| 封裝： | LEAD FREE, TQFP-44 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 74K |
| 代理商： | IDT5V995PFGI |
9
INDUSTRIAL TEMPERATURE RANGE
IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
REF
FB
Q
OTHER Q
INVERTED Q
REF DIVIDED BY 2
REF DIVIDED BY 4
t
REF
t
SKEW2
t
SKEW3, 4
t
SKEW1, 3, 4
t
SKEW2, 4
t
SKEW3, 4
t
SKEW3, 4
t
SKEW2
t
SKEWPR
t
SKEW0, 1
t
CCJH, HA,
M, L, LA
t
ODCV
t
ODCV
t
RPWH
t
RPWL
t
SKEWPR
t
SKEW0, 1
t
(
φ)
AC TIMING DIAGRAM
NOTES:
PE:
The AC Timng Diagramapplies to PE=V
DD
. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge
of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
The time between the earliest and the latest output transition among all outputs for which the same t
U
delay has been selected when all are loaded with 20pF and termnated
with 75
to V
DDQ
/2.
The skew between a pair of outputs (xQ
0
and xQ
1
) when all eight outputs are selected for 0t
U
.
The skew between outputs when they are selected for 0t
U
.
The output-to-output skew between any two devices operating under the same conditions (V
DDQ
,
V
DD
, ambient temperature, air flow, etc.)
The deviation of the output froma 50% duty cycle. Output pulse width variations are included in t
SKEW2
and t
SKEW4
specifications.
t
PWH
is measured at 2V.
t
PWL
is measured at 0.8V.
t
ORISE
and t
OFALL
are measured between 0.8V and 2V.
t
LOCK
:
The time that is required before synchronization is achieved. This specification is valid only after V
DD
/V
DDQ
is stable and within normal operating limts. This parameter
is measured fromthe application of a new signal or frequency at REF or FB until t
PD
is within specified limts.
Skew:
t
SKEWPR
:
t
SKEW0
:
t
DEV
:
t
ODCV
:
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| IDT5V995PFGI8 | 功能描述:IC CLK DVR PLL 3.3V PROGR 44TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ II 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT600 | 制造商:DRUCK 功能描述:MOISTURE TRAP |
| IDT60ALVCH16823PA | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD |
| IDT60LVC162374APA | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V CMOS 16-BIT EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD |
| IDT60LVC162374APF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V CMOS 16-BIT EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD |
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