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參數(shù)資料
| 型號： | IDT5V995PFGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK |
| 中文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP44 |
| 封裝： | LEAD FREE, TQFP-44 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 74K |
| 代理商： | IDT5V995PFGI |
7
INDUSTRIAL TEMPERATURE RANGE
IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
SWITCHING CHARACTERISTICS OV ER OPERATING RANGE
Symbol
F
NOM
t
RPWH
t
RPWL
t
U
t
SKEWPR
t
SKEW0
t
SKEW1
t
SKEW2
t
SKEW3
t
SKEW4
t
DEV
Parameter
VCO Frequency Range
REF Pulse Width HIGH
(1)
REF Pulse Width LOW
(1)
Programmable Skew Time Unit
Zero Output Matched-Pair Skew (xQ
0
, xQ
1
)
(2,3)
Zero Output Skew (All Outputs)
(4)
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)
(5)
Output Skew (Rise-Fall, Nomnal-Inverted, Divided-Divided)
(5)
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)
(5)
Output Skew (Rise-Fall, Nomnal-Divided, Divided-Inverted)
(2)
Device-to-Device Skew
(2,6)
Static Phase Offset (FS = L, M H) (FB Divide-by-n = 1, 2, 3)
(7)
Static Phase Offset (FS = H)
(7)
Static Phase Offset (FS = M)
(7)
Static Phase Offset (FS = L) (FB Divide-by-n = 1, 2, 3, 4, 5, 6)
(7)
Static Phase Offset (FS = L) (FB Divide-by-n = 8, 10, 12)
(7)
Output Duty Cycle Variation from50%
Output HIGH Time Deviation from50%
(8)
Output LOW Time Deviation from50%
(9)
Output Rise Time
Output Fall Time
PLL Lock Time
(10,11)
Cycle-to-Cycle Output Jitter (peak-to-peak)
(divide by 1 output frequency, FS = H, FB divide-by-n=1,2)
Cycle-to-Cycle Output Jitter (peak-to-peak)
(divide by 1 output frequency, FS = H, FB divide-by-n=any)
Cycle-to-Cycle Output Jitter (peak-to-peak)
(divide by 1 output frequency, FS = M)
Cycle-to-Cycle Output Jitter (peak-to-peak)
(divide by 1 output frequency, FS = L, F
REF
> 3MHz)
Cycle-to-Cycle Output Jitter (peak-to-peak)
(divide by 1 output frequency, FS = L, F
REF
< 3MHz)
Min.
See Programmable Skew Range and Resolution Table
2
—
2
—
See Control Summary Table
—
50
—
0.1
—
0.1
—
0.2
—
0.15
—
0.3
—
—
0.25
—
0.25
—
0.5
—
0.7
—
1
—
1
0
—
—
—
—
0.15
0.7
0.15
0.7
—
—
—
—
Typ.
Max.
Unit
—
—
ns
ns
185
0.25
0.25
0.5
0.5
0.9
0.75
0.25
0.25
0.5
0.7
1
1
1.5
2
1.5
1.5
0.5
100
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
(
φ
)1-3
(
φ
)H
t
(
φ
)M
t
(
φ
)L1-6
t
(
φ
)L8-12
t
ODCV
t
PWH
t
PWL
t
ORISE
t
OFALL
t
LOCK
t
CCJH
t
CCJHA
—
—
150
t
CCJM
—
—
150
ps
t
CCJL
—
—
200
t
CCJLA
—
—
300
NOTES:
1. Refer to Input Timng Requirements table for more detail.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same t
U
delay has been selected when all are loaded with the specified
load.
3. t
SKEWPR
is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t
U
.
4. t
SK(0)
is the skew between outputs when they are selected for 0t
U
.
5. There are 3 classes of outputs: Nomnal (multiple of t
U
delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-
by-4 mode). Test condition: nF0:1=MMis set on unused outputs.
6. t
DEV
is the output-to-output skew between any two devices operating under the same conditions (V
DDQ
, V
DD
, ambient temperature, air flow, etc.)
7. t
φ
is measured with REF input rise and fall times (from0.8V to 2V) of 0.5ns. Measured from1.5V on REF to 1.5V on FB.
8. Measured at 2V.
9. Measured at 0.8V.
10. t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
DD
/V
DDQ
is stable and within normal operating limts. This parameter
is measured fromthe application of a new signal or frequency at REF or FB until t
PD
is within specified limts.
11. Lock detector may be unreliable for input frequencies less than approximately 4MHz, or for input signals which contain significant jitter.
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