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參數(shù)資料
| 型號(hào)： | IDT5V926 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | SINGLE OUTPUT CLOCK GENERATOR |
| 中文描述： | 單輸出時(shí)鐘發(fā)生器 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 45K |
| 代理商： | IDT5V926 |
2
INDUSTRIAL TEMPERATURE RANGE
IDT5V926
SINGLE OUTPUT CLOCK GENERATOR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REFE
X
1
/REF
X
2
V
DD
V
DDQ
GND
Q
REF
V
DDQ
S
1
OE
GND
V
DDQ
GND
Q
OUT
V
DDQ
S
0
PIN CONFIGURATION
TSSOP
TOP VIEW
CRY S TAL S PE CIFICAT ION
The crystal oscillators should be fundamental mode quartz crystals:
overtone crystals are not suitable. Crystal frequency should be specified
for parallel resonance with 50
maximumequivalent series resonance.
Crystal tuning capacitors should be connected fromX
1
/REF to GND and from
X
2
to GND.
ABSOLUTE MAX IMUM RATINGS
(1)
Symbol
Description
V
DD
/V
DDQ
Supply Voltage to Ground
V
I
Input Voltage
I
O
Output Current
T
STG
Storage Temperature
T
J
Junction Temperature
Max.
Unit
V
V
mA
°C
°C
– 0.5 to +4.6
– 0.5 to +4.6
±50
– 65 to +150
150
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximumrating
conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Name Type
Description
S[
1:0
]
OE
I
Three level divider/mode select pins. Float to MID.
I
Output enable bar. Outputs Q
OUT
and Q
REF
are tristated when
HIGH. Set
OE
LOW for normal operation (has internal pull-
down).
Q
REF
enable input. Q
REF
stopped LOW when HIGH. When set
REFE
LOW, the Q
REF
is enabled (has internal pull-down).
REFE
I
X
1
/REF
X
2
I
I
Crystal oscillator input or clock input
Crystal oscillator output. Leave unconnected for clock input.
Q
OUT
O
Output at N*REF frequency
Q
REF
O
Output at REF frequency
V
DDQ
PWR
Power supply for the device outputs. Connect to V
DD
on PCB.
V
DD
PWR
Power supply for the device core and inputs. Connect to V
DD
on PCB.
Ground supply
GND
PWR
NOTES:
1.
H = HIGH
M= MEDIUM
L = LOW
Test mode for low frequency testing. In this mode, REF clock bypasses the VCO (VCO powered down) and the crystal oscillator is powered down.
2.
DIV IDE SELECTION TABLE
(1)
S1
S0
Divide-by-N Value
Mode
L
L
2
PLL
L
M
3
PLL
L
H
4
PLL
M
L
4.25
PLL
M
M
5
PLL
M
H
6
PLL
H
L
6.25
PLL
H
M
8
PLL
H
H
TEST
TEST
(2)
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