參數(shù)資料
型號(hào)： IDT5T9891NLI8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 33/37頁(yè)
文件大?。?/td> 0K
描述： IC CLK DRIVER 2.5V PLL 68-VFQFPN
產(chǎn)品變化通告： Product Discontinuation 05/Jan/2011
標(biāo)準(zhǔn)包裝： 2,500
類型： PLL 時(shí)鐘驅(qū)動(dòng)器
PLL： 帶旁路
輸入： eHSTL，HSTL，LVPECL，LVTTL
輸出： eHSTL，HSTL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:10
差分 - 輸入:輸出： 是/是
頻率 - 最大： 250MHz
除法器/乘法器： 是/無(wú)
電源電壓： 2.3 V ~ 2.7 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 68-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 68-VFQFPN（10x10）
包裝： 帶卷 (TR)
其它名稱： 5T9891NLI8
5
INDUSTRIALTEMPERATURERANGE
IDT5T9891
EEPROMPROGRAMMABLE2.5VPROGRAMMABLESKEWPLLDIFFERENTIAL
PIN DESCRIPTION, CONTINUED
Symbol
I/O
Type
Description
REF_SEL
I
LVTTL(1)
Reference clock select. When LOW, selects REF0 and REF0/VREF0. When HIGH, selects REF1 and REF1/VREF1.
nsOE
I
LVTTL(1)
Synchronousoutputenable/disable. Eachoutputs'senable/disablestatecanbecontrolledeitherwiththensOEpinorthroughJTAG
or I2C programming, corresponding bits 52 - 56. When the nsOE is HIGH or the corresponding Bit (52 - 56) is 1, the output will be
synchronouslydisabled.Whenthe nsOEisLOWandthecorrespondingBit(52-56)is0,theoutputwillbeenabled. (SeeJTAG/I2C
SerialConfigurationtable.)
QFB
O
Adjustable(2) Feedbackclockoutput
QFB
O
Adjustable(2) Complementaryfeedbackclockoutput
nQ
O
Adjustable(2) Clockoutputs
nQ
O
Adjustable(2) Complementaryclockoutputs
PLL_EN
I
LVTTL(1)
PLL enable/disable control. The PLL's enable/disable state can be controlled either with the PLL_EN pin or through JTAG or I2C
programming, corresponding Bit 57. When PLL_EN is HIGH or the corresponding Bit 57 is 1, the PLL is disabled and REF[1:0]goes
to all outputs. When PLL_EN is LOW and the corresponding Bit 57 is 0, the PLL will be active.
PD
I
LVTTL(1)
Power down control. When PD is LOW, the inputs are disabled and internal switching is stopped. The OMODE pin in conjunction
with the corresponding Bit 59 selects whether the outputs are gated LOW/HIGH or tri-stated. When OMODE is HIGH or Bit 59 is 1,
Bit 58 determines the level at which the outputs stop. When Bit 58 is 0/1, the nQ and QFB are stopped in a HIGH/LOW state, while
the nQ and QFB are stopped in a LOW/HIGH state. When OMODE is LOW and Bit 59 is 0, the outputs are tri-stated. Set PD HIGH
fornormaloperation. (SeeJTAG/I2CSerialConfigurationtable.)
LOCK
O
LVTTL
PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to
the inputs. The output will be 2.5V LVTTL. (For more information on application specific use of the LOCK pin, please see AN237.)
OMODE
I
LVTTL(1)
Outputdisablecontrol. UsedinconjunctionwithnsOEand PD. Theoutputs'disablestatecanbecontrolledeitherwiththeOMODE
pinorthroughJTAGorI2Cprogramming,correspondingBit59. WhenOMODEisHIGHorthecorrespondingBit59is1,theoutputs'
disablestatewillbegatedandBit58willdeterminethelevelatwhichtheoutputsstop. WhenBit58is0/1,the nQandQFBarestopped
in a HIGH/LOW state, while the nQ and QFB are stopped in a LOW/HIGH state. When OMODE is LOW and its corresponding bit
59 is 0, the outputs disable state will be the tri-state. (See JTAG/I2C Serial Configurations tables.)
TRST/SEL
I/I
LVTTL/
TRST- Active LOW input to asynchronously reset the JTAG boundary-scan circuit.
LVTTL(4,5)
SEL-Selectprogramminginterfacecontrolforthedual-functionpins. WhenHIGH,thedual-functionpinsaresetforJTAGprogramming.
WhenLOW,thedual-functionpinsaresetforI2CprogrammingandtheJTAGinterfaceisasynchronouslyplacedintheTestLogicReset
state.
TDO/ADDR1 O/I
LVTTL/
TDO-Serialdataoutputpinforinstructionsaswellastestandprogrammingdata. DataisshiftedinonthefallingedgeofTCLK. The
pinistri-statedifdataisnotbeingshiftedoutofthedevice.
ADDR1-UsedtodefineauniqueI2Caddressforthisdevice. OnlyforI2Cprogramming. (SeeJTAG/I2CSerialInterfaceDescription.)
TMS/ADDR0
I/I
LVTTL/
TMS-InputpinthatprovidesthecontrolsignaltodeterminethetransitionsoftheJTAGTAPcontrollerstatemachine. Transitionswithin
thestatemachineoccurattherisingedgeofTCLK. Therefore,TMSmustbesetupbeforetherisingedgeofTCLK. TMSisevaluated
on the rising edge of TCLK.
ADDR0-UsedtodefineauniqueI2Caddressforthisdevice. OnlyforI2Cprogramming. (SeeJTAG/I2CSerialInterfaceDescription.)
TCLK/SCLK
I/I
LVTTL/
TCLK - The clock input to the JTAG BST circuitry.
SCLK - Serial clock for I2C programming
TDI/SDA
I/I
LVTTL/
TDI - Serial input pin for instructions as well as test and programming data. Data is shifted in on the rising edge of TCLK.
SDA - Serial data (see JTAG/I2C Serial Description table)
VDDQN
PWR
Power supply for each pair of outputs. When using 2.5V LVTTL, 1.8V LVTTL, HSTL, or eHSTL outputs, VDDQNshould be set to its
correspondingoutputs(seeFrontBlockDiagram). Whenusing2.5VLVTTLoutputs,VDDQNshouldbeconnectedtoVDD.
VDD
PWR
Powersupplyforphaselockedloop,lockoutput,inputs,andotherinternalcircuitry
GND
PWR
Ground
3-Level(3,4,5)
LVTTL(4,5)
NOTES:
1. Pins listed as LVTTL inputs can be configured to accept 1.8V or 2.5V signals through the use of the I2C/JTAG programming, bit 61. (See JTAG/I2C Serial Description.)
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQN voltage.
3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.
4. The JTAG (TDO, TMS, TCLK, and TDI) and I2C (ADDR1, ADDR0, SCLK, and SDA) signals share the same pins (dual-function pins) for which the TRST/SEL pin will select between
the two programming interfaces.
5. JTAG and I2C pins accept 2.5V signals. The JTAG input pins (TMS, TCLK, TDI, TRST) will also accept 1.8V signals.
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