I2
參數(shù)資料
型號(hào)： IDT5T9891NLI8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 20/37頁
文件大?。?/td> 0K
描述： IC CLK DRIVER 2.5V PLL 68-VFQFPN
產(chǎn)品變化通告： Product Discontinuation 05/Jan/2011
標(biāo)準(zhǔn)包裝： 2,500
類型： PLL 時(shí)鐘驅(qū)動(dòng)器
PLL： 帶旁路
輸入： eHSTL，HSTL，LVPECL，LVTTL
輸出： eHSTL，HSTL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:10
差分 - 輸入:輸出： 是/是
頻率 - 最大： 250MHz
除法器/乘法器： 是/無
電源電壓： 2.3 V ~ 2.7 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 68-VFQFPN（10x10）
包裝： 帶卷 (TR)
其它名稱： 5T9891NLI8
27
INDUSTRIALTEMPERATURERANGE
IDT5T9891
EEPROMPROGRAMMABLE2.5VPROGRAMMABLESKEWPLLDIFFERENTIAL
I2C SERIAL INTERFACE CONTROL
The I2C interface permits the configuration of the IDT5T9891. The
IDT5T9891isaread/writeslavedevicemeetingPhilipsI2Cbusspecifications.
The I2C bus is controlled by a master device that generates the serial clock
SCLK,controlsbusaccess,andgeneratestheSTARTandSTOPconditions
while the device works as a slave. Both master and slave can operate as a
transmitter and receiver but the master device determines which mode is
activated.
BUS CONDITIONS
Datatransferonthebuscanonlybeinitiatedwhenthebusisnotbusy. During
datatransfer,thedataline(SDA)mustremainstablewhenevertheclockline
(SCLK) is high. Changes in the data line while the clock line is high will be
interpreted by the device as a START or STOP condition. The following bus
conditions are defined by the I2C bus protocol and are illustrated in figure 1.
NOT BUSY
Boththedata(SDA)andclock(SCLK)linesremainhightoindicatethebus
is not busy.
STARTDATATRANSFER
AhightolowtransitionoftheSDAlinewhiletheSCLKinputishighindicates
aSTARTcondition. AllcommandstothedevicemustbeprecededbyaSTART
condition.
STOP DATA TRANSFER
A low to high transition of the SDA line while SCLK is held high indicates a
STOP condition. All commands to the device must be followed by a STOP
condition.
DATA VALID
The state of the SDA line represents valid data if the SDA line is stable for
thedurationofthehighperiodoftheSCLKlineafteraSTARTconditionoccurs.
The data on the SDA line must be changed only during the low period of the
SCLKsignal. Thereisoneclockpulseperdatabit. Eachdatatransferisinitiated
by a START condition and terminated with a STOP condition.
ACKNOWLEDGE
When addressed, the receiving device is required to generate an
Acknowledge after each byte is received. The master device must generate
anextraclockpulsetocoincidewiththeAcknowledgebit. Theacknowledging
device must pull the SDA line low during the high period of the master
acknowledge clockpulse. Setup and hold times mustbe taken intoaccount.
I2C BUS OPERATION
TheIDT5T9891I2CinterfacesupportsStandard-Mode(100kHz)andFast-
Mode(400kHz)datatransferrates. Dataistransferredinbytesinsequential
orderfromthelowesttohighestbyte. AftergeneratingaSTARTcondition,the
bus master broadcasts a 7-bit slave address followed by a read/write bit.
I2C ADDRESS
A7
A6
A5
A4
A3
A2
A1
11
0
1
X
Address A0 is the read/write bit and is set to ‘0’ for writes and ‘1’ for reads.
The ADDR0 and ADDR1 tri-level pins allow the last three bits of the 7-bit
address to be defined by the user.
ADDR1
ADDR0
A3
A2
A1
LOW
0
LOW
MID
0
1
LOW
HIGH
0
1
0
MID
LOW
0
1
MID
1
0
MID
HIGH
1
0
1
HIGH
LOW
1
0
HIGH
MID
1
HIGH
1
0
WRITE OPERATION
(see I2C Interface Definition for ProgWrite)
Toinitiateawriteoperation(ProgWrite),theread/writebitissetto‘0’. During
thewriteoperation,thefirsttwobytestransferredmustbetheDeviceAddress
followed by the Command Code. The internal programming registers of the
deviceignorethesefirsttwobytes. ThesubsequentbytesaretheDataBytes,
whichtotaltwelve. AlltwelveDataBytesmustbewrittenintothedeviceduring
the write operation in order for the internal programming registers to be
updated. IfaSTOPconditionisgeneratedbeforethe12thDataByte,theinternal
programming registers will remain unchanged to prevent an invalid PLL
configuration. AnAcknowledgebythedevicebetweeneachbytemustoccur
before the next byte is sent. After the transfer of the 12th Data Byte, an
Acknowledge signal will be sent to the bus master after which it will generate
a STOP condition. Once the STOP condition has occurred, the internal
programming registers of the device will be updated.
READOPERATION
(see I2C Interface Definition for ProgRead)
Toinitiateareadoperation(ProgRead),theread/writebitissetto‘1’. During
thereadoperation,therewillbeatotaloffourteendatabytesreturnedfollowing
anAcknowledgeofthedeviceaddress. ThefirsttwodatabytesaretheIDByte
andaReservedByte,inthatorder. Thesubsequentbytesarethesametwelve
Data Bytes that were written during the write operation. The read back can
be terminated at any time by issuing a STOP condition.
I2C ID BYTE
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
00
0
1
相關(guān)PDF資料
PDF描述
IDT5V2305NRGI8 IC CLK BUFF 1:5 200MHZ 16-VFQFPN
IDT5V2310NRGI8 IC CLK BUFF 1:10 200MHZ 20VFQFPN
IDT5V49EE501NLGI IC CLOCK GEN PLL 500MHZ 24QFN
IDT5V49EE502NLGI8 IC PLL CLK GEN 200MHZ 24VQFN
IDT5V49EE702NDGI8 IC PLL CLK GEN 200MHZ 28VQFN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT5T989X-982X-M1 功能描述:KIT FOR 5T989X-982X RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081
IDT5T9950APFGI 功能描述:IC CLK BUFFER/DVR 1:10 32TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ II JR 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT
IDT5T9950APFGI8 功能描述:IC CLK BUFFER/DVR 1:10 32TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ II JR 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT
IDT5T9950PFGI 功能描述:IC CLK BUFFER/DVR 1:10 32TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ II JR 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR
IDT5T9950PFGI8 功能描述:IC CLK BUFFER/DVR 1:10 32TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ II JR 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*