參數(shù)資料
型號(hào)： IDT5T9821NLI8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 11/36頁(yè)
文件大?。?/td> 0K
描述： IC CLK DRIVER ZD PLL 68-VFQFPN
產(chǎn)品變化通告： Product Discontinuation 05/Jan/2011
標(biāo)準(zhǔn)包裝： 2,500
類型： PLL 時(shí)鐘驅(qū)動(dòng)器
PLL： 帶旁路
輸入： eHSTL，HSTL，LVPECL，LVTTL
輸出： eHSTL，HSTL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:5
差分 - 輸入:輸出： 是/是
頻率 - 最大： 250MHz
除法器/乘法器： 是/無
電源電壓： 2.3 V ~ 2.7 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 68-VFQFPN（10x10）
包裝： 帶卷 (TR)
其它名稱： 5T9821NLI8
19
INDUSTRIALTEMPERATURERANGE
IDT5T9821
EEPROMPROGRAMMABLE2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Alloutputsatthedifferentinterfacelevel
Symbol
Parameter
Min.
Typ.
Max
Unit
FNOM
VCO Frequency Range
see JTAG/I2C Serial Configurations: VCO Frequency Range table
tRPW
Reference Clock Pulse Width HIGH or LOW
1
—
ns
tFPW
Feedback Input Pulse Width HIGH or LOW
1
—
ns
tSK(O)
Output Skew (Rise-Rise, Fall-Fall, Nominal)(1,2)
—
250
ps
tSK1(
ω)
MultipleFrequencySkew(Rise-Rise,Fall-Fall,Nominal-Divided,Divided-Divided)(1,2,3)
—
500
ps
tSK2(
ω)
MultipleFrequencySkew(Rise-Fall,Nominal-Divided,Divided-Divided)(1,2,3)
—
500
ps
tSK1(INV)
InvertingSkew(Nominal-Inverted)(1,2)
——
500
ps
tSK2(INV)
InvertingSkew(Rise-Rise,Fall-Fall,Rise-Fall,Inverted-Divided)(1,2,3)
—
500
ps
tSK(PR)
Process Skew(1,2,4)
——
400
ps
t(
φ)
REF Input to FB Static Phase Offset(5)
-200
—
200
ps
tODCV
Output Duty Cycle Variation from 50%(11,12)
1.8VLVTTL
-475
—
475
ps
2.5VLVTTL
-375
—
375
tORISE
OutputRiseTime(6)
HSTL / eHSTL / 1.8V LVTTL
—
1.2
ns
2.5VLVTTL
—
1
tOFALL
OutputFallTime(6)
HSTL / eHSTL / 1.8V LVTTL
—
1.2
ns
2.5VLVTTL
—
1
tL
Power-up PLL Lock Time(7)
——
4
ms
tL(
ω)
PLLLockTimeAfterInputFrequencyChange(7)
——
1
ms
tL(PD)
PLL Lock Time After Asserting PD Pin(7)
——
1
ms
tL(REFSEL1)
PLL Lock Time After Change in REF_SEL(7,9)
—
100
s
tL(REFSEL2)
PLL Lock Time After Change in REF_SEL (REF1 and REF0are different frequency)(7)
——
1
ms
tJIT(CC)
Cycle-to-CycleOutputJitter(peak-to-peak)(2,8)
—
—
100
ps
tJIT(PER)
PeriodJitter(peak-to-peak)(2,8)
——
100
ps
tJIT(HP)
HalfPeriodJitter(peak-to-peak)(2,8,10)
——
200
ps
tJIT(DUTY)
DutyCycleJitter(peak-to-peak)(2,8)
——
150
ps
VOX
HSTLandeHSTLDifferentialTrueandComplementaryOutputCrossingVoltageLevel
VDDQN/2 - 150 VDDQN/2 VDDQN/2 + 150 mV
NOTES:
1. Skew is the time between the earliest and latest output transition among all outputs when all outputs are loaded with the specified load.
2. For differential LVTTL outputs, the measurement is made at VDDQN/2, where the true outputs are only compared with other true outputs and the complementary outputs are only
compared to other complementary outputs. For differential HSTL/eHSTL outputs, the measurement is made at the crossing point (VOX) of the true and complementary signals.
3. There are three classes of outputs: nominal (zero delay), inverted, and divided (divide-by-2 or divide-by-4 mode).
4. tSK(PR) is the output to corresponding output skew between any two devices operating under the same conditions (VDD and VDDQN, ambient temperature, air flow, etc.).
5. t(
φ) is measured with REF and FB the same type of input, the same rise and fall times. For 1.8V / 2.5V LVTTL input and output, the measurement is taken from VTHI on REF
to VTHI on FB. For HSTL / eHSTL input and output, the measurement is taken from the crosspoint of REF/REF to the crosspoint of FB/FB. All outputs are set to zero delay,
FB input divider is set to divide-by-one, and Bit 60 = 1.
6. Output rise and fall times are measured between 20% to 80% of the actual output voltage swing.
7. tL, tL(
ω), tL(REFSEL1), tL(REFSEL2), and tL(PD) are the times that are required before the synchronization is achieved. These specifications are valid only after VDD/VDDQN is stable and
within the normal operating limits. These parameters are measured from the application of a new signal at REF or FB, or after PD is (re)asserted until t(
φ) is within specified
limits.
8. The jitter parameters are measured with all outputs selected for zero delay, FB input divider is set to divide-by-one, and Bit 60 = 1.
9. Both REF inputs must be the same frequency, but up to ±180° out of phase.
10. For HSTL/eHSTL outputs only.
11. For LVTTL outputs only.
12. tODCV is measured with all outputs selected for zero delay.
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IDT5T9890NLI 功能描述:IC CLK DRIVER 2.5V PLL 68-VFQFPN RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
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