參數(shù)資料
型號(hào): IDT23S09E
廠商: Integrated Device Technology, Inc.
英文描述: 3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
中文描述: 3.3零延遲時(shí)鐘緩沖器,擴(kuò)頻兼容
文件頁(yè)數(shù): 3/8頁(yè)
文件大小: 65K
代理商: IDT23S09E
3
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT23S09E
3.3V ZERO DELAY CLOCK BUFFER
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol
Parameter
V
IL
Input LOW Voltage Level
V
IH
Input HIGH Voltage Level
I
IL
Input LOW Current
I
IH
Input HIGH Current
V
OL
Output LOW Voltage
Conditions
Min.
2
Max.
0.8
50
100
0.4
Unit
V
V
μA
μA
V
V
IN
= 0V
V
IN
= V
DD
Standard Drive
High Drive
Standard Drive
High Drive
REF = 0MHz (S2 = S1 = H)
Unloaded Outputs at
66.66MHz, SEL inputs at V
DD
or GND
I
OL
= 8mA
I
OL
= 12mA (-1H)
I
OH
= -8mA
I
OH
= -12mA (-1H)
V
OH
Output HIGH Voltage
2.4
V
I
DD_PD
I
DD
Power Down Current
Supply Current
12
32
μA
mA
SWITCHING CHARACTERISTICS (23S09E-1) - COMMERCIAL
(1,2)
Symbol
t
1
Parameter
Conditions
Min.
10
10
40
1
Typ.
50
0
5
0
Max.
200
100
60
2.5
2.5
250
±
350
8.7
700
200
Unit
MHz
Output Frequency
10pF Load
30pF Load
Measured at 1.4V, F
OUT
= 66.66MHz
Measured between 0.8V and 2V
Measured between 0.8V and 2V
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 in PLL bypass mode (IDT23S09E only)
Measured at V
DD
/2 on the CLKOUT pins of devices
Measured at 66.66MHz, loaded outputs
Duty Cycle = t
2
÷
t
1
Rise Time
Fall Time
Output to Output Skew
Delay, REF Rising Edge to CLKOUT Rising Edge
(2)
Delay, REF Rising Edge to CLKOUT Rising Edge
(2)
Device-to-Device Skew
Cycle-to-Cycle Jitter
%
ns
ns
ps
ps
ns
ps
ps
t
3
t
4
t
5
t
6A
t
6B
t
7
t
J
t
LOCK
PLL Lock Time
Stable power supply, valid clock presented on REF pin
1
ms
NOTES:
1. REF Input has a threshold voltage of V
DD
/2.
2. All parameters specified with loaded outputs.
Symbol
V
DD
T
A
C
L
Parameter
Min.
3
0
Max.
3.6
70
30
10
7
Unit
V
°
C
pF
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance < 100MHz
Load Capacitance 100MHz - 200MHz
Input Capacitance
C
IN
pF
OPERATING CONDITIONS - COMMERCIAL
FUNCTION TABLE
(1)
S2
L
L
H
S1
L
H
L
CLKA
Tri-State
Driven
Driven
CLKB
Tri-State
Tri-State
Driven
CLKOUT
(2)
Driven
Driven
Driven
Output Source
PLL
PLL
REF
PLL Shut Down
N
N
Y
H
H
Driven
Driven
Driven
PLL
N
NOTES:
1. H = HIGH Voltage Level.
L = LOW Voltage Level
2. This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew between the REF and the output.
相關(guān)PDF資料
PDF描述
IDT23S09E-1DC 3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
IDT23S09E-1DCI 3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT23S09E_09 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
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