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參數(shù)資料
| 型號(hào)： | ICSVF2509BGT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2509 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-24 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 151K |
| 代理商： | ICSVF2509BGT |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICSVF2509B
1036C— 07/13/05
Block Diagram
3.3V Phase-Lock Loop Clock Driver
Pin Configuration
The ICSVF2509B is a high performance, low skew, low
jitter clock driver.It uses a phase lock loop (PLL) technology
to align, in both phase and frequency, the CLKIN signal
with the CLKOUT signal. It is specifically designed for use
with synchronous SDRAMs. The ICSVF2509B operates
at 3.3V VCC and drives up to nine clock loads.
One bank of five outputs and one bank of four outputs
provide nine low-skew, low-jitter copies of CLKIN. Output
signal duty cycles are adjusted to 50 percent, independent
of the duty cycle at CLKIN. Each bank of outputs can be
enabled or disabled separately via control (OEA and OEB)
inputs. When the OE inputs are high, the outputs align in
phase and frequency with CLKIN; when the OE inputs are
low, the outputs are disabled to the logic low state.
The ICSVF2509B does not require external RC filter
components.The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.The
buffer mode shuts off the PLL and connects the input
directly to the output buffer. This buffer mode, the
ICSVF2509B can be use as low skew fanout clock buffer
device. The ICSVF2509B comes in 24 pin 173mil Thin
Shrink Small-Outline package (TSSOP) package.
Meets or exceeds PC133 registered DIMM
specification1.1
Spread Spectrum Clock Compatible
Distributes one clock input to one bank of ten outputs
Operating frequency 20MHz to 200MHz
External feedback input (FBIN) terminal is used to
synchrionize the outputs to the clock input
No external RC network required
Operates at 3.3V Vcc
Plastic 24-pin 173mil TSSOP package
24 Pin TSSOP
4.40 mm. Body, 0.65 mm. pitch
FBIN
CLKIN
AVCC
OEA
OEB
PLL
CLKA0
FBOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB0
CLKB1
CLKB2
CLKB3
AGND
VCC
CLKA0
CLKA1
CLKA2
GND
CLKA3
CLKA4
VCC
OEA
FBOUT
CLKIN
VCC
CLKB0
CLKB1
GND
CLKB2
CLKB3
VCC
OEB
FBIN
AVCC
IC
SVF2509B
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