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參數(shù)資料
| 型號(hào)： | ICSVF2510BGILFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2510 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, MO-153, TSSOP-24 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 123K |
| 代理商： | ICSVF2510BGILFT |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICSVF2510
0722B—05/06/04
Block Diagram
3.3V Phase-Lock Loop Clock Driver
Pin Configuration
The ICSVF2510 is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the CLKIN signal with
the CLKOUT signal. It is specifically designed for use with
synchronous SDRAMs.The ICSVF2510 operates at 3.3V
VCC and drives up to ten clock loads.
One bank of ten outputs provide low-skew, low-jitter
copies of CLKIN. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLKIN.
Outputs can be enabled or disabled via control (OE)
inputs. When the OE inputs are high, the outputs align in
phase and frequency with CLKIN; when the OE inputs are
low, the outputs are disabled to the logic low state.
The ICSVF2510 does not require
external RC filter
components.The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.The
test mode shuts off the PLL and connects the input
directly to the output buffer.This test mode, the ICSVF2510
can be use as low skew fanout clock buffer device. The
ICSVF2510 comes in 24 pin 173mil Thin Shrink Small-
Outline package (TSSOP) package.
Meets or exceeds PC133 registered DIMM
specification1.1
Spread Spectrum Clock Compatible
Distributes one clock input to one bank of ten outputs
Operating frequency 20MHz to 200MHz
External feedback input (FBIN) terminal is used to
synchrionize the outputs to the clock input
No external RC network required
Operates at 3.3V Vcc
Plastic 24-pin 173mil TSSOP package
Industrial temperature version available
FBIN
CLKIN
AVCC
OE
PLL
CLK1
CLK0
FBOUT
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
AGND 1
24 CLKIN
VCC 2
23 AVCC
CLK0 3
22 VCC
CLK1 4
21 CLK9
CLK2 5
20 CLK8
GND 6
19 GND
GND 7
18 GND
CLK3 8
17 CLK7
CLK4 9
16 CLK6
VCC 10
15 CLK5
OE 11
14 VCC
FBOUT 12
13 FBIN
24 Pin TSSOP
4.40 mm. Body, 0.65 mm. Pitch
IC
S
V
F
2510
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