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參數(shù)資料
| 型號： | ICSSSTV32852yHT |
| 英文描述： | DDR 24-Bit to 48-Bit Registered Buffer |
| 中文描述： | 復(fù)員24位到48位注冊緩沖區(qū) |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 129K |
| 代理商： | ICSSSTV32852YHT |
5
ICSSSTV32852
0513F—05/13/03
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
MAX
200
2.7
4.5
4
f
clock
t
PD
t
RST
t
SL
Clock frequency
Clock to output time
Reset to output time
Output slew rate
Setup time, fast slew rate
2, 4
MHz
ns
ns
V/ns
ns
1.9
1
0.50
Setup time, slow slew rate
3, 4
0.70
ns
Hold time, fast slew rate
2, 4
Hold time, slow slew rate
3, 4
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
0.30
0.50
ns
ns
4 - CLK/CLK# signal input slew rate of 1V/ns.
V
DD
= 2.5V ±0.2V
UNITS
PARAMETERS
Data before CLK
↑
, CLK#
↓
Data after CLK
↑
, CLK#
↓
SYMBOL
t
S
T
h
Notes:
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
From
(Input)
(Output)
MIN
200
1.9
TYP
MAX
fmax
t
PD
t
phl
MHz
ns
ns
CLK, CLK#
RESET#
Q
Q
2.7
4.5
SYMBOL
V
DD
= 2.5V ±0.2V
UNITS
To
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