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參數(shù)資料
| 型號(hào)： | ICSSSTV32852yHT |
| 英文描述： | DDR 24-Bit to 48-Bit Registered Buffer |
| 中文描述： | 復(fù)員24位到48位注冊(cè)緩沖區(qū) |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 129K |
| 代理商： | ICSSSTV32852YHT |
4
ICSSSTV32852
0513F—05/13/03
Electrical Characteristics - DC
T
A
= 0 - 70°C; V
DD
= 2.5 +/-0.2V, V
DDQ
=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL
PARAMETERS
V
IK
I
I
= -18mA
I
OH
= -100μA
I
OH
= -16mA
I
OL
= 100μA
I
OL
= 16mA
I
I
All Inputs
V
I
= V
DD
or GND
Standby (Static)
RESET# = GND
V
I
= V
IH(AC)
or V
IL(AC)
,
RESET# = V
DD
RESET# = V
DD
,
V
I
= V
IH(AC)
or V
IL(AC)
,
CLK and CLK# switching
50% duty cycle.
RESET# = V
DD
,
V
I
= V
IH(AC)
or V
IL (AC)
,
CLK and CLK# switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
r
OH
Output High
r
OL
Output Low
[r
OH
-
r
OL
] each
separate bit
Data Inputs
CLK and CLK#
Notes:
1. Guaranteed by design, not 100% tested in production.
V
DDQ
2.3V
MIN
TYP
MAX
-1.2
UNITS
2.3V - 2.7V
2.3V
2.3V - 2.7V
2.3V
2.7V
V
DDQ
- 0.2
2.05
0.2
0.20
±5
0.01
μA
μA
Operating (Static)
40
mA
Dynamic operating
(clock only)
35
μA/clock
MHz
Dynamic Operating
(per each data input)
7
μA/ clock
MHz/data
2.3V - 2.7V
2.3V - 2.7V
12
10
r
O(D)
2.5V
4
2.5
2.5
3.5
3.5
C
i
I
OL
= 20mA
I
O
= 20mA, T
A
= 25°C
V
OH
V
OL
I
DD
I
DDD
I
O
= 0
CONDITIONS
2.5V
2.5V
V
I
= V
REF
±350mV
V
ICR
= 1.25V, V
I(PP)
= 360mV
pF
I
OH
= -20mA
V
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