
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
1626
09/17/09
ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
3
Advance Information
Pin Description for OE_INV = 0
PIN #
PIN NAME
PIN
TYPE
DESCRIPTION
INTERNAL
PULL UP
OR PULL
DOWN?
1
VDD
PWR
Power supply, nominal 3.3V
N/A
2
SRC_IN
IN
0.7 V Differential SRC TRUE input
N/A
3
SRC_IN#
IN
0.7 V Differential SRC COMPLEMENTARY input
N/A
4
GND
PWR
Ground pin.
N/A
5
VDD
PWR
Power supply, nominal 3.3V
N/A
6
DIF_1
OUT
0.7V differential true clock output
N/A
7
DIF_1#
OUT
0.7V differential Complementary clock output
N/A
8
OE_1
IN
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
PULL UP
9
DIF_2
OUT
0.7V differential true clock output
N/A
10
DIF_2#
OUT
0.7V differential Complementary clock output
N/A
11
VDD
PWR
Power supply, nominal 3.3V
N/A
12
BYPASS#_SSCG
IN
Input to select Bypass(fan-out) or SSCG (PLL) mode
0 = Bypass mode, 1= SSCG mode
PULL UP
13
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
N/A
14
SDATA
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
N/A
15
PD#
IN
Asynchronous active low input pin used to power down the device. The
internal clocks are disabled and the VCO and the crystal osc. (if any) are
stopped.
PULL UP
16
DIF_STOP#
IN
Active low input to stop differential output clocks.
PULL UP
17
SPREAD_EN
IN
Asynchronous, active high input to enable spread spectrum functionality.
PULL UP
18
VDD
PWR
Power supply, nominal 3.3V
N/A
19
DIF_5#
OUT
0.7V differential Complementary clock output
N/A
20
DIF_5
OUT
0.7V differential true clock output
N/A
21
OE_6
IN
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
PULL UP
22
DIF_6#
OUT
0.7V differential Complementary clock output
N/A
23
DIF_6
OUT
0.7V differential true clock output
N/A
24
VDD
PWR
Power supply, nominal 3.3V
N/A
25
OE_INV
IN
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
N/A
26
IREF
OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
N/A
27
GNDA
PWR
Ground pin for the PLL core.
N/A
28
VDDA
PWR
3.3V power for the PLL core.
N/A