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參數(shù)資料
| 型號： | ICS98ULPA877AKLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 1.8V Low-Power Wide-Range Frequency Clock Driver |
| 中文描述： | 98ULPA SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MLF-40 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 172K |
| 代理商： | ICS98ULPA877AKLF-T |
6
ICS98ULPA877A
Advance Information
1177C—05/23/07
NOTE: The PLL must be able to handle spread spectrum induced skew.
NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not
required to meet the other timing parameters. (Used for low speed system debug.)
NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters.
NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal, within the value specificied by the Static Phase Offset (t
), after power-up.
During
normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock
of its feedback signal to its reference signal when CK and CK# go to a logic low state, enter the power-down mode
and later return to active operation. CK and CK# may be left floating after they have been driven low for one
complete clock cycle.
Timing Requirements
Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;
Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
Max clock frequency
freq
op
Application Frequency
Range
Input clock duty cycle
d
tin
CONDITIONS
MIN
95
MAX
410
UNITS
MHz
1.8V+0.1V @ 25°C
freq
App
1.8V+0.1V @ 25°C
160
410
MHz
40
60
%
CLK stabilization
T
STAB
15
μs
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