參數(shù)資料
型號: ICS952702
英文描述: Programmable Timing Control Hub for K7 System
中文描述: 可編程定時控制中心的k7的系統(tǒng)
文件頁數(shù): 3/17頁
文件大小: 160K
代理商: ICS952702
3
Integrated
Circuit
Systems, Inc.
ICS952702
0795D—05/06/05
Pin Description
PIN #
PIN NAME
PIN
TYPE
PWR
I/O
I/O
I/O
PWR
IN
OUT
PWR
OUT
OUT
PWR
IN
PWR
I/O
I/O
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDDREF
Ref, XTAL power supply, nominal 3.3V
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Ground pin for the REF outputs.
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin for the ZCLK outputs
3.3V Hyperzip clock output.
3.3V Hyperzip clock output.
Power supply for ZCLK clocks, nominal 3.3V
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low.
Power supply for PCI clocks, nominal 3.3V
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
PCI clock output.
PCI clock output.
Ground pin for the PCI outputs
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin for the PCI outputs
Ground pin for the 48MHz outputs
Selectable 24 or 48MHz clock output / Latched select input for 24/48MHz output. 0=24MHz,
1 = 48MHz.
Selectable 12 or 48MHz clock output / Latched select input for 12/48MHz output. 0=12MHz,
1 = 48MHz.
Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
Power supply for AGP clocks, nominal 3.3V
AGP clock output
AGP clock output
Ground pin for the AGP outputs
Asynchronous active low input pin used to power down the device into a low power state. The
internal clocks are disabled and the VCO and the crystal are stopped. The latency of the
power down will not be greater than 1.8ms.
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
3.3V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
Supply for CPU clocks, 3.3V nominal
"Complememtary" clocks of differential pair CPU outputs. These open drain outputs need an
external 1.5V pull-up.
True clock of differential pair CPU outputs. These open drain outputs need an external 1.5V
pull-up.
Ground pin for the CPU outputs
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
This signal is active low.
True clock of differential pair CPU outputs. These open drain outputs need an external 1.5V
pull-up.
Stops all CPUCLK besides the free running clocks
Ground pin for the IOAPIC outputs.
IOAPIC clock outputs, norminal 2.5V.
IOAPIC clock outputs, norminal 2.5V.
Power pin for the IOAPIC outputs. 2.5V.
** Internal Pull-Down Resistor
**FS0/REF0
**FS1/REF1
**FS4/REF2
GNDREF
X1
X2
GNDZ
ZCLK0
ZCLK1
VDDZ
*PCI_STOP#
VDDPCI
**FS2/PCICLK_F0
*FS3/PCICLK_F1
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
GND48
26
24_48MHz/SEL24#_48MHz**
I/O
27
12_48MHz/SEL12#_48MHz*
I/O
28
29
30
31
32
AVDD48
VDDAGP
AGPCLK1
AGPCLK0
GNDAGP
PWR
PWR
OUT
OUT
PWR
33
PD#*
IN
34
35
36
37
38
SDATA
SCLK
AVDD
AGND
VDDCPU
I/O
IN
PWR
PWR
PWR
39
CPUCLKODC0
OUT
40
CPUCLKODT0
OUT
41
GNDCPU
PWR
42
RESET#
OUT
43
CPUCLKODT1
OUT
44
45
46
47
48
CPU_STOP#*
GNDAPIC
IOAPIC0
IOAPIC1
VDDLAPIC
* Internal Pull-Up Resistor
IN
PWR
OUT
OUT
PWR
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ICS952703BFLFT 功能描述:IC TIMING CTRL HUB K7 48-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:TCH™ 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP (0.240",6.10mm 寬) 供應商設備封裝:64-TSSOP 包裝:管件