參數(shù)資料
型號(hào)： ICS950812YGLFT
英文描述： Frequency Generator with 200MHz Differential CPU Clocks
中文描述： 頻率發(fā)生器200MHz的CPU的時(shí)鐘差分
文件頁(yè)數(shù)： 27/29頁(yè)
文件大?。?/td> 225K
代理商： ICS950812YGLFT
27
ICS950812
0542G—08/21/03
Power Down De-Assertion Mode
The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the ramping
of the power supply until the time that stable clocks are output from the clock chip. If the I
2
C Bit 6 of Byte 0 is programmed
to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.
Test Configuration Diagrams
CPU 1.0V Configuration test load board termination
TLA
TLB
R
REF
=221 Ohms
1%
MULTSEL Pin must be Low
Rs=33 Ohms
1%
Rs=33 Ohms
1%
Rp=63.4 Ohms
1%
Rp=63.4 Ohms
1%
Rdif=475 Ohms
1%
2pF
5%
2pF
5%
CPUCLKT test
point
CPUCLKC test
point
CLK408
CPU 0.7V Configuration test load board termination
TLA
TLB
MULTSEL Pin must be High
Rs=33 Ohms
5%
Rs=33 Ohms
5%
Rp=49.9 Ohms
1%
Rp=49.9 Ohms
1%
Rset=475 Ohms
1%
2pF
5%
2pF
5%
CPUCLKT test
point
CPUCLKC test
point
CLK408
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