參數(shù)資料
型號(hào): ICS950104yFT
英文描述: Programmable System Clock Chip for PIII Processor
中文描述: 可編程系統(tǒng)時(shí)鐘芯片的PIII處理器
文件頁(yè)數(shù): 18/19頁(yè)
文件大小: 222K
代理商: ICS950104YFT
18
ICS950104
Advance Information
Third party brands and names are the property of their respective owners.
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the
ICS94252
. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS94252.
3. All other clocks continue to run undisturbed.
PCICLK
CPUCLK
PD# (High)
PCI_STOP# (High)
CPU_STOP#
INTERNAL
CPUCLK
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參數(shù)描述
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