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| 型號(hào)： | ICS9248YG-195LF-T |
| 英文描述： | Frequency Generator & Integrated Buffers for PENTIUM II/III & K6 |
| 中文描述： | 頻率發(fā)生器 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 160K |
| 代理商： | ICS9248YG-195LF-T |
第1頁(yè)第2頁(yè)第3頁(yè)當(dāng)前第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)
4
ICS9248-195
0375D—02/02/04
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched register values will be inverted from pin values. Default latch condition is for all latched inputs to
be floating (pulled up via internal resistor) at power-up.
Byte 2: Active/Inactive Register (1 = enable, 0 = disable)
t
t
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
B
#
n
D
W
1
1
1
1
1
1
1
1
P
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D
)
D
)
D
)
D
)
D
)
D
)
D
)
D
o
D
F
_
K
L
(
6
K
L
(
5
K
L
(
4
K
L
(
3
K
L
(
2
K
L
(
1
K
L
(
0
K
L
7
6
5
4
3
2
1
0
7
1
1
1
1
1
1
8
/
E
/
E
/
E
/
E
/
E
/
E
/
E
/
E
(
C
C
C
C
C
C
C
C
I
I
I
I
I
I
I
I
C
C
C
C
C
C
C
C
P
P
P
P
P
P
P
P
8
7
3
2
1
0
Byte 1: Active/Inactive Register (1 = enable, 0 = disable)
Byte 3: Active/Inactive Register (1 = enable, 0 = disable)
t
t
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
B
#
n
D
W
1
1
0
0
1
1
1
1
P
n
o
D
)
e
v
R
F
_
K
L
C
U
P
C
)
e
v
R
(
)
e
v
R
(
F
_
M
A
R
D
S
2
K
L
C
U
P
C
1
K
L
C
U
P
C
0
K
L
C
U
P
C
7
6
5
4
3
2
1
0
-
6
-
-
9
2
3
5
(
4
)
D
/
E
(
3
4
4
4
)
D
)
D
)
D
)
D
/
E
/
E
/
E
/
E
(
(
(
(
t
t
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
B
#
n
D
W
1
0
0
0
1
1
1
1
P
n
o
D
)
e
v
R
)
e
v
R
)
e
v
R
)
e
v
R
(
7
M
A
R
D
S
6
M
A
R
D
S
5
M
A
R
D
S
4
M
A
R
D
S
7
6
5
4
3
2
1
0
-
-
-
-
8
9
1
3
2
3
(
(
(
(
2
2
)
D
)
D
)
D
)
D
/
E
/
E
/
E
/
E
(
(
(
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