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參數(shù)資料
| 型號： | ICS9110-02CS14LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GENERATOR 14SOIC |
| 標準包裝： | 2,500 |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | TTL，晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 130MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 14-SOIC |
| 包裝： | 帶卷 (TR) |
5
AV9110
Output Divider Turth Tables
1
D
O
C0
D
O
C
X
/
K
L
C
e
d
i
v
i
D
t
u
p
t
u
O
)
X
(
00
1
01
2
10
4
11
8
Table 2
1
D
O
C0
D
O
C
O
C
V
e
d
i
v
i
D
t
u
p
t
u
O
)
R
(
00
1
01
2
10
4
11
8
Table 3
Programming the PLL
The AV9110 has a wide operating range but it is recommended that it is operated within the following limits:
The AV9110 is a classical PLL circuit and the VCO output frequency is given by:
fVCO =
NV fREF
M
Where N = VCO divided, 3 to 127
M =m Reference divide, 3 to 127
V = Perscale, 1 or 8
The 2 output drivers then give the following frequencies:
fCLK =
fVCO
R
= NV fREF
MR
or fREF (output mixable by bit 17)
fCLK/X =
=
fVCLK
X
Where R, X = output dividers 1, 2, 4 or 8
fVCO
RX
Notes:
1. Output frequency accuracy will depend solely on input reference frequency accuracy.
2. For output frequencies below 125 MHz, it is recommended that the VCO output divide, R, should be 2 or greater. This will
give improved duty cycle.
3. The minimum output frequency step size is approximately 0.2% due to the divider range provided.
f
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F
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M
2
3
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