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參數(shù)資料
| 型號： | ICS874005AGLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI EXPRSS/JITT ATTEN 24TSSOP |
| 標準包裝： | 2,500 |
| 系列： | HiPerClockS™, FemtoClock™, PCI Express® (PCIe) |
| 類型： | 扇出緩沖器（分配），漂移衰減器 |
| PLL： | 是 |
| 主要目的： | PCI Express（PCIe） |
| 輸入： | HCSL，LVDS，LVHSTL，LVPECL，SSTL |
| 輸出： | LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 160MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 874005AGLFT |
ICS874005AG REVISION B JANUARY 12, 2012
6
2012 Integrated Device Technology, Inc.
ICS874005 Data Sheet
PCI EXPRESS JITTER ATTENUATOR
APPLICATIONS INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2
shows how a differential input can be wired to ac-
cept single ended levels. The reference voltage V
REF = VDD/2 is
generated by the bias resistors R1 and R2. The bypass ca-
pacitor (C1) is used to help filter noise on the DC bias. This
bias circuit should be located as close to the input pin as
possible. The ratio of R1 and R2 might need to be adjusted
to position the V
REF
in the center of the input voltage swing.
For example, if the input clock swing is 2.5V and
VDD = 3.3V,
R1 and R2 value should be adjusted to set V
REF at 1.25V. The
values below are for when both the single ended swing and
V
DD are at the same voltage. This configuration requires that
the sum of the output impedance of the driver (Ro) and the
series resistance (Rs) equals the transmission line imped-
ance. In addition, matched termination at the input will at-
tenuate the signal in half. This can be done in one of two
ways. First, R3 and R4 in parallel should equal the transmis-
sion line impedance. For most 50W applications, R3 and
R4 can be 100W. The values of the resistors can be in-
creased to reduce the loading for slower and weaker LVCMOS
driver. When using single-ended signaling, the noise rejec-
tion benefits of differential signaling are reduced. Even
though the differential input can handle full rail LVCMOS sig-
naling, it is recommended that the amplitude be reduced.
The datasheet specifies a lower differential amplitude, how-
ever this only applies to differential signals. For single-ended
applications, the swing can be larger, however V
IL cannot be
less than -0.3V and V
IH cannot be more than VCC + 0.3V.
Though some of the recommended components might not
be used, the pads should be placed in the layout. They can
be utilized for debugging purposes. The datasheet specifi-
cations are characterized and guaranteed by using a differ-
ential signal.
Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
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