參數(shù)資料
型號(hào): ICS854057
英文描述: 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION
中文描述: 4:1或2:1的LVDS脈多與內(nèi)部輸入終端
文件頁數(shù): 9/13頁
文件大小: 256K
代理商: ICS854057
854057AG
www.icst.com/products/hiperclocks.html
REV. A JULY 18, 2005
9
Integrated
Circuit
Systems, Inc.
ICS854057
4:1
OR
2:1 LVDS C
LOCK
M
ULTIPLEXER
WITH
I
NTERNAL
I
NPUT
T
ERMINATION
LVPECL I
NPUT
WITH
B
UILT
-I
N
50
Ω
T
ERMINATIONS
I
NTERFACE
The PCLK /nPCLK with built-in 50
Ω
terminations accepts
LVDS, LVPECL, LVHSTL, CML, SSTL and other differential
signals. Both V
SWING
and V
OH
must meet the V
and V
input requirements. Figures 3A to 3E show interface
examples for the HiPerClockS PCLK/nPLCK input with built-in
50
Ω
terminations driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to
confirm the driver termination requirements.
F
IGURE
3A. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
WITH
B
UILT
-
IN
50
Ω
D
RIVEN
BY
AN
LVDS D
RIVER
F
IGURE
3B. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
WITH
B
UILT
-
IN
50
Ω
D
RIVEN
BY
AN
LVPECL D
RIVER
IN
nIN
VT
2.5V
LVDS
3.3V or 2.5V
Zo = 50 Ohm
Zo = 50 Ohm
Receiver
With
Built-In
50 Ohm
Zo = 50 Ohm
Receiver
With
Built-In
50 Ohm
Zo = 50 Ohm
IN
nIN
VT
2.5V
2.5V
R1
18
2.5V LVPECL
F
IGURE
3E. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
WITH
B
UILT
-
IN
50
Ω
D
RIVEN
BY
AN
SSTL D
RIVER
F
IGURE
3C. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
WITH
B
UILT
-
IN
50
Ω
D
RIVEN
BY
AN
O
PEN
C
OLLECTOR
CML D
RIVER
F
IGURE
3D. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
WITH
B
UILT
-
IN
50
Ω
D
RIVEN
BY
A
CML D
RIVER
WITH
B
UILT
-I
N
50
Ω
P
ULLUP
Zo = 50 Ohm
2.5V
Zo = 50 Ohm
IN
nIN
VT
Receiver
With
Built-In
50 Ohm
2.5V
CML - Open Collector
IN
nIN
VT
Receiver
With
Built-In
50 Ohm
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
CML - Built-in 50 Ohm Pull-up
2.5V
2.5V
2.5V
SSTL
R1
25
R2
25
IN
VT
nIN
Receiver With Built-In 50
Ω
Zo = 50 Ohm
Zo = 50 Ohm
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ICS8543BG LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER
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