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參數(shù)資料
| 型號： | ICS843034AYLFT |
| 英文描述： | MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| 中文描述： | 多速率3.3伏，2.5伏的LVPECL頻率合成器 |
| 文件頁數(shù)： | 18/23頁 |
| 文件大?。?/td> | 250K |
| 代理商： | ICS843034AYLFT |
843034AY
www.icst.com/products/hiperclocks.html
REV. A JULY 25, 2005
18
Integrated
Circuit
Systems, Inc.
ICS843034
F
EMTO
C
LOCKS
M
ULTI
-R
ATE
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
A
PPLICATION
S
CHEMATIC
E
XAMPLE
Figure 8shows a schematic example of using an ICS843034.
In this example, the CLK/nCLK input is driven by a 3.3V
LVPECL driver. The data sheet also shows the CLK/nCLK
input driven by various types of drivers. The crystal inputs are
parallel resonant crystal with load capacitor CL=18pF. The
frequency fine tuning capacitors C1 and C2 are 22pF. This
schematic example shows hardwired logic control input
handling. The logic inputs can also be driven by 3.3V LVCMOS
drivers. It is recommended to have one decouple capacitor
per power pin. In general, the decoupling capacitor values
are ranged from 0.01uF to 0.1uF. Each decoupling capacitor
should be located as close as possible to the power pin. The
low pass filter R9, C11 and C16 for clean analog supply
3.3V
Zo = 50 Ohm
Zo = 50
Set Logic
Input to
'0'
C2
22p
To Logic
Input
pins
VCCO_REF
Alternative
Termination
Exmaple
VCCO_REF=3.3V
VCC
LVCMOS
VCCA
C8
C9
R8
43
R11
50
R12
50
C11
0.01u
R3
50
VCC
X1
CL=18pF
R1
50
C3
22p
Set Logic
Input to
'1'
R7
82.5
RD2
1K
R4
133
RU2
SPARE
C4
22p
VCC
R9
10
C6
0.1u
R2
50
R10
50
C1
22p
C7
+
-
Zo = 50 Ohm
Zo = 50 Ohm
VCCO=3.3V
Zo = 50 Ohm
Logic Input Pin Examples
Zo = 50 Ohm
+
-
VCC
VCCO
VCC
RD1
SPARE
RU1
1K
LVPECL
VCC=3.3V
C5
R5
82.5
U1
1
2
3
4
5
6
7
8
9
10
11
12
1
1
1
1
1
1
1
2
2
2
2
2
36
35
34
33
32
31
30
29
28
27
26
25
4
4
4
4
4
4
4
4
4
3
3
3
M8
NB0
NB2
OE_A
OE_B
VCC
NA0
NA2
VEE
T
V
F
n
V
F
n
V
R
V
P
V
X_OUT1
X_X_IN1
TESX_IN0
SEL1
SEL0
VCCA
S_DATA
S_CLOCK
MR
M
M
M
M
M
M
M
M
V
n
n
C
Zo = 50
C16
10u
R6
133
To Logic
Input
pins
VCCO
X1
CL=18pF
F
IGURE
8. ICS843034 A
PPLICATION
S
CHEMATIC
E
XAMPLE
should also be located as close to the VCCA pin as possible.
Only two examples of 3.3V LVPECL termination are shown in
this schematic example. Additional LVPECL terminations can
be found in the LVPECL Termination Application Note. The
data sheet also shows 2.5V LVPECL terminations. The
REF_CLK is LVCMOS driver with 7
Ω
output impedance. Series
termination for REF_CLK is shown in the example. Additional
LVCMOS termination can be found in the LVCMOS Application
Note. If the REF_CLK is not used, it is recommended to disable
this output by setting REF_OE to logic low. To disable
REF_CLK, REF_OE pin can be left floating (default logic low
by internal 51K pull down) or pull down using an external
1K
Ω
resistor.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS843034AYT | MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| ICS843071AGI | FEMTOCLOCKS⑩ CRYSTAL-TO- LVPECL CLOCK GENERATOR |
| ICS843071AGILF | FEMTOCLOCKS⑩ CRYSTAL-TO- LVPECL CLOCK GENERATOR |
| ICS843071AGILFT | FEMTOCLOCKS⑩ CRYSTAL-TO- LVPECL CLOCK GENERATOR |
| ICS843071AGIT | FEMTOCLOCKS⑩ CRYSTAL-TO- LVPECL CLOCK GENERATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS843034AYT | 制造商:ICS 制造商全稱:ICS 功能描述:MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| ICS843051 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR |
| ICS8430-51 | 制造商:ICS 制造商全稱:ICS 功能描述:600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843051AG | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR |
| ICS843051AGLF | 功能描述:IC CLK GEN GIG ETH LVPECL 8TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
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