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參數資料
| 型號： | ICS843034A01 |
| 英文描述： | FEMTOCLOCKS⑩ MULTI-RATE LVPECL FREQUENCY SYNTHESIZER |
| 中文描述： | FEMTOCLOCKS⑩多速率的LVPECL頻率合成器 |
| 文件頁數： | 16/22頁 |
| 文件大?。?/td> | 244K |
| 代理商： | ICS843034A01 |
843034AY-01
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 28, 2005
16
Integrated
Circuit
Systems, Inc.
ICS843034-01
F
EMTO
C
LOCKS
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
V
CC
- 2V
50
Ω
50
Ω
RTT
Z
o
= 50
Ω
Z
o
= 50
Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o
= 50
Ω
Z
o
= 50
Ω
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUTx and nFOUTx are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
6B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
6A. LVPECL O
UTPUT
T
ERMINATION
drive 50
Ω
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 6A and 6B
show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
Ω
resistor can be tied from XTAL_IN to ground.
CLK I
NPUT
:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1k
Ω
resistor can be tied from the CLK input to
ground.
CLK/nCLK I
NPUT
:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
Ω
resistor can be tied from
CLK to ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
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| ICS843034AY-01 | FEMTOCLOCKS⑩ MULTI-RATE LVPECL FREQUENCY SYNTHESIZER |
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| ICS843034AYL | MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| ICS843034AYLF | MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ICS843034AY | 制造商:ICS 制造商全稱:ICS 功能描述:MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| ICS843034AY-01 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ MULTI-RATE LVPECL FREQUENCY SYNTHESIZER |
| ICS843034AY-01LF | 功能描述:IC CLK SYNTHESIZER LVPECL 48LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ICS843034AY-01LFT | 功能描述:IC CLK SYNTHESIZER LVPECL 48LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標準包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數:1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC 包裝:管件 |
| ICS843034AY-01T | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ MULTI-RATE LVPECL FREQUENCY SYNTHESIZER |
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