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參數(shù)資料
| 型號： | ICS7973DI147 |
| 英文描述： | LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER |
| 中文描述： | 低偏移，1至12個LVCMOS / LVTTL時鐘倍頻/零延遲緩沖器 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 287K |
| 代理商： | ICS7973DI147 |
87973DYI-147
www.icst.com/products/hiperclocks.html
11
REV. A AUGUST 26, 2003
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS87973I-147 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
, V
, and V
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 3 illustrates how
a 10
resistor along with a 10
μ
F and a .01
μ
F bypass
capacitor should be connected to each V
DDA
pin.
F
IGURE
3. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
μ
F
.01
μ
F
3.3V
.01
μ
F
V
DD
Figure 4 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
4. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
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