- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360755 > ICS6953BI147 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER PDF資料下載
參數(shù)資料
| 型號： | ICS6953BI147 |
| 英文描述： | DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER |
| 中文描述： | 差分至的LVCMOS / LVTTL零延遲緩沖器 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大小： | 265K |
| 代理商： | ICS6953BI147 |
86953BYI-147
www.icst.com/products/hiperclocks.html
REV. B APRIL 23, 2004
9
Integrated
Circuit
Systems, Inc.
ICS86953I-147
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS / LVTTL Z
ERO
D
ELAY
B
UFFER
Other
signals
C5
C16
R7
50 Ohm
Trace
VDD
VIA
50 Ohm
Trace
R1
GND
C3
Pin 1
U1
R2
VCCA
C2
C11
C4
C1
F
IGURE
4B. PCB B
OARD
L
AYOUT
F
OR
ICS86953I-147
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on
the component side is preferred. This can reduce unwanted in-
ductance between the decoupling capacitor and the power pin
caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
DDA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The 50
output traces should have same length.
Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The series termination resistors should be located as
close to the driver pins as possible.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS7151A | Spread Spectrum Clock Generator |
| ICS7151AM-50 | Spread Spectrum Clock Generator |
| ICS7151AM-50LF | Spread Spectrum Clock Generator |
| ICS7151AM-50LFT | Spread Spectrum Clock Generator |
| ICS7151AM-50T | Spread Spectrum Clock Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS70-1 | 制造商:Thomas & Betts 功能描述:Cable Accessories Compression Splice Aluminum |
| ICS71-1 | 制造商:Thomas & Betts 功能描述:Cable Accessories Compression Splice Aluminum |
| ICS7151 | 制造商:ICS 制造商全稱:ICS 功能描述:Spread Spectrum Clock Generator |
| ICS7151A | 制造商:ICS 制造商全稱:ICS 功能描述:Spread Spectrum Clock Generator |
| ICS7151AM-50 | 功能描述:IC CLOCK GENERATOR 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。