參數(shù)資料
型號(hào): ICS6953BI147
英文描述: DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
中文描述: 差分至的LVCMOS / LVTTL零延遲緩沖器
文件頁數(shù): 6/13頁
文件大?。?/td> 265K
代理商: ICS6953BI147
86953BYI-147
www.icst.com/products/hiperclocks.html
REV. B APRIL 23, 2004
6
Integrated
Circuit
Systems, Inc.
ICS86953I-147
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS / LVTTL Z
ERO
D
ELAY
B
UFFER
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS86953I-147 provides sepa-
rate power supplies to isolate any high switching noise from the
outputs to the internal PLL. V
and V
should be individually
connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required. Figure 2
illustrates how a 10
resistor along with a 10μF and a .01μF
bypass capacitor should be connected to each V
DDA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
μ
F
.01
μ
F
3.3V
.01
μ
F
V
DDO
A
PPLICATION
I
NFORMATION
Figure 1shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R2
1K
V_REF
C1
0.1u
R1
1K
Single Ended Clock Input
PCLK
nPCLK
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