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| 型號： | ICS680G-01T |
| 英文描述： | Networking Clock Synthesizer and Zero Delay Buffer |
| 中文描述： | 網(wǎng)絡時鐘合成器和零延遲緩沖器 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 107K |
| 代理商： | ICS680G-01T |
Networking Clock Synthesizer and Zero Delay Buffer
MDS 680-01 F
7
Revision 020305
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
ICS680-01
Package Outline and Package Dimensions
(24-pin TSSOP, 173 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
“LF” denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
Part / Order Number
ICS680G-01
ICS680G-01T
ICS680G-01LF
ICS680G-01LFT
Marking
680G-01
680G-01
680G-01LF
680G-01LF
Shipping Packaging
Tubes
Tape and Reel
Tubes
Tape and Reel
Package
24-pin TSSOP
24-pin TSSOP
24-pin TSSOP
24-pin TSSOP
Temperature
0 to +70
°
C
0 to +70
°
C
0 to +70
°
C
0 to +70
°
C
INDEX
AREA
1 2
24
D
E1
E
SEATING
PLANE
A1
A
A2
e
- C -
b
.10 (.004)
C
c
L
Millimeters
Inches
Symbol
A
A1
A2
b
C
D
E
E1
e
L
α
Min
—
0.05
0.80
0.19
0.09
7.70
6.40 BASIC
4.30
0.65 Basic
0.45
0
°
Max
1.20
0.15
1.05
0.30
0.20
7.90
Min
—
0.002
0.032
0.007
0.0035
0.303
0.252 BASIC
0.169
0.0256 Basic
.018
0
°
Max
.047
0.006
0.041
0.012
0.008
0.311
4.50
0.177
0.75
8
°
.030
8
°
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