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| 型號： | ICS680G-01T |
| 英文描述： | Networking Clock Synthesizer and Zero Delay Buffer |
| 中文描述： | 網(wǎng)絡(luò)時(shí)鐘合成器和零延遲緩沖器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 107K |
| 代理商： | ICS680G-01T |
Networking Clock Synthesizer and Zero Delay Buffer
MDS 680-01 F
6
Revision 020305
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
ICS680-01
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%
, Ambient Temperature 0 to +70
°
C
Parameter
Symbol
Input Frequency
f
IN
Note 1: Measured with a 15 pF load.
Note 2: Duty cycle is configuration dependent. Most configurations are min 45% / max 55%.
Note 3: Skew is measured at 1.4 V on rising edges with a 33 MHz ICLK.
Conditions
Min.
Typ.
25
33
33
1.5
1.5
Max.
Units
MHz
MHz
MHz
ns
ns
%
ms
X1
ICLK
Q0 to Q3, QFB, Note 1
20% to 80%, Note 1
80% to 20%, Note 1
at VDD/2, Note 2
PLL lock-time from
power-up to 1% of final
frequency
PDTS goes high until
stable CLK outputs at
1% of final frequency
Configuration
dependent
Deviation from mean.
Configuration
dependent.
Measured at VDD/2,
Note 3
QFB, Q0 to Q3, Note 3
Output Frequency
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Power-up Time
f
OUT
t
OR
t
OF
t
D
40
60
10
2
ms
One Sigma Clock Period Jitter
50
ps
Maximum Absolute Jitter
t
ja
±200
ps
QFB to ICLK Skew
t
PD
-350
350
Pin-to-pin Skew
-250
250
ps
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