參數(shù)資料
型號(hào): ICS673M-01T
英文描述: PLL Building Block
中文描述: 鎖相環(huán)積木
文件頁(yè)數(shù): 9/9頁(yè)
文件大?。?/td> 73K
代理商: ICS673M-01T
ICS673-01
PLL Building Block
MDS 673-01 D
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126(408)295-9800tel www.icst.com
9
Revision 022500
Printed 11/15/00
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
Ordering Information
Part/Order Number
ICS673M-01
ICS673M-01T
ICS673M-01I
ICS673M-01IT
Marking
ICS673M-01
ICS673M-01
ICS673M-01I
ICS673M-01I
Shipping packaging
tubes
tape and reel
tubes
tape and reel
Package
16 pin SOIC
16 pin SOIC
16 pin SOIC
16 pin SOIC
Temperature
0 to 70 °C
0 to 70 °C
-40 to 85 °C
-40 to 85 °C
16 pin SOIC narrow
Inches
Min
0.0532
0.0040
0.0130
0.0075
0.3859
0.1497
.050 BSC
0.2284
0.0099
0.0160
Millimeters
Min
1.35
0.10
0.33
0.19
9.80
3.80
1.27 BSC
5.80
0.25
0.41
Symbol
A
A1
B
C
D
E
e
H
h
L
Max
0.0688
0.0098
0.0200
0.0098
0.3937
0.1574
Max
1.75
0.24
0.51
0.24
10.00
4.00
0.2440
0.0195
0.0500
6.20
0.50
1.27
B
D
E
H
e
A1
C
A
h x 45°
L
INDEX
AREA
1
2
Package Outline and Package Dimensions
(
For current dimensional specifications, see JEDEC Publication No. 95.)
相關(guān)PDF資料
PDF描述
ICS673-01 PLL Building Block
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ICS680G-01 Networking Clock Synthesizer and Zero Delay Buffer
ICS680G-01LF Networking Clock Synthesizer and Zero Delay Buffer
ICS680G-01LFT Networking Clock Synthesizer and Zero Delay Buffer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS674-01 制造商:ICS 制造商全稱:ICS 功能描述:User Configurable Divider
ICS674R-01 功能描述:IC DIVIDER USER CONFIG 28-SSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器,PLL,頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器,零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:133.3MHz 除法器/乘法器:是/無(wú) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG
ICS674R-01I 功能描述:IC DIVIDER USER CONFIG 28-SSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器,PLL,頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器,零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:133.3MHz 除法器/乘法器:是/無(wú) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG
ICS674R-01ILF 功能描述:IC DIVIDER USER CONFIG 28-SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器,PLL,頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS,LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP(7x7) 包裝:帶卷 (TR)
ICS674R-01ILFT 功能描述:IC DIVIDER USER CONFIG 28-SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器,PLL,頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS,LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP(7x7) 包裝:帶卷 (TR)