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參數(shù)資料
| 型號(hào)： | ICS671M-05I |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 176K |
| 代理商： | ICS671M-05I |
ICS671-05
MDS 671-05 F
1
Revision 031004
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l
www.icst.com
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
Description
The ICS671-05 is a low phase noise, high-speed PLL
based, 8-output, low skew zero delay buffer. Based on
ICS’ proprietary low jitter Phase-Locked Loop (PLL)
techniques, the device provides eight low skew outputs
at speeds up to 133 MHz at 3.3 V. The outputs can be
generated from the PLL (for zero delay), or directly
from the input (for testing), and can be set to tri-state
mode or to stop at a low level. For normal operation as
a zero delay buffer, any output clock is tied to the FBIN
pin.
ICS manufactures the largest variety of clock
generators and buffers and is the largest clock supplier
in the world.
Features
Clock outputs from 10 to 133 MHz
Zero input-output delay
Eight low skew (<200 ps) outputs
Device-to-device skew <700 ps
Low jitter (<200 ps)
Full CMOS outputs with 25mA output drive capability
at TTL levels
5V tolerant FBIN and CLKIN pins
Tri-state mode for board-level testing
Advanced, low power, sub-micron CMOS process
Operating voltage of 3.3V
Industrial temperature range available
Packaged in 16-pin SOIC and TSSOP packages
Block Diagram
CLKA4
CLKB1
CLKA3
CLKB2
CLKB3
CLKA2
CLKA1
CLKB4
Control
Logic
S2, S1
CLKIN
FBIN
2
VDD
2
GND
2
1
0
Clock
Synthesis
PLL
Feedback is shown from CLKB4 for
illustration, but may not come from any output
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS671M-05ILF | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS671G-15 | 671 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| ICS671M-02ILF | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS671M-02I | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| ICS671M-02ILF | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS671M-06I | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| ICS671M-06ILF | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| ICS671M-06ILFT | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| ICS671M-06IT | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| ICS672-01 | 制造商:ICS 制造商全稱:ICS 功能描述:QuadraClock⑩ Quadrature Delay Buffer |
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