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| 型號： | ICS671M-03IT |
| 英文描述： | 3.3 Volt Zero Delay, Low Skew Buffer |
| 中文描述： | 3.3伏零延遲，低偏移緩沖 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 47K |
| 代理商： | ICS671M-03IT |
ICS671-03
3.3 Volt Zero Delay, Low Skew Buffer
MDS 671-03 A
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408) 295-9800 tel www.icst.com
3
Revision 072501
PRELIMINARY INFORMATION
Parameter
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Inputs and Clock Outputs
CLKIN and FBIN Inputs
Electrostatic Discharge
Ambient Operating Temperature
Soldering Temperature
Junction temperature
Storage temperature
DC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)
Operating Voltage, VDD
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, CMOS level
Operating Supply Current, IDD (Note 2)
Power Down Supply Current, IDD
Conditions
Minimum Typical
Maximum
Units
Referenced to GND
Referenced to GND
-0.5
-0.5
-0.5
2000
-40
7
V
V
VDD+0.5
5.5
85
260
150
150
MIL-STD-883
V
°C
°C
°C
°C
Max of 10 seconds
-65
3.00
2
3.60
V
V
V
V
V
V
IOH=-12 mA
IOL=12 mA
IOH=-8mA
No Load, S2=1, S1=1
CLKIN=0, S2=0, S1=1
CLKIN=0 (Note 3)
Each output
S2, S1, FBIN
0.8
2.4
0.4
VDD-0.4
70
mA
mA
mA
mA
pF
1.3
1.3
±50
5
Short Circuit Current
Input Capacitance
AC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)
Input Clock Frequency
Output Clock Frequency
Output Clock Rise Time, CL=30pF
Output Clock Fall Time, CL=30pF
Output Clock Duty Cycle, VDD=3.3V
Device to Device Skew, equally loaded
Output to Output Skew, equally loaded
Input to Output Skew, FBIN to CLKA4, S1=1, S0 =1
(Note 2)
See table on page 2
See table on page 2
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
rising edges at VDD/2
rising edges at VDD/2
10
10
133
133
1.5
1.25
55
700
200
MHz
MHz
ns
ns
%
ps
ps
45
50
rising edges at VDD/2
±250
300
1.0
ps
ps
ps
ms
Maximum Absolute Jitter
Cycle to Cycle Jitter, 30pF loads
PLL Lock Time (Note 4)
130
Electrical Specifications
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the
device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may
affect device reliability.
2. With CLKIN = 100 MHz, FBIN to CLKA4, all outputs at 100 MHz.
3. When there is no clock signal present at CLKIN, the ICS671-03 will enter a power down mode. The PLL is
stopped and the outputs are tri-state.
4. With VDD at a steady state, and valid clocks at CLKIN and FBIN.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS671-06 | 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| ICS671M-06I | 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| ICS671M-06ILF | 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| ICS671M-06ILFT | 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| ICS671M-06IT | 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS671M-06I | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| ICS671M-06ILF | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| ICS671M-06ILFT | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| ICS671M-06IT | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 VOLT ZERO DELAY, LOW SKEW BUFFER |
| ICS672-01 | 制造商:ICS 制造商全稱:ICS 功能描述:QuadraClock⑩ Quadrature Delay Buffer |
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