參數(shù)資料
型號: ICS671M-03IT
英文描述: 3.3 Volt Zero Delay, Low Skew Buffer
中文描述: 3.3伏零延遲,低偏移緩沖
文件頁數(shù): 2/4頁
文件大小: 47K
代理商: ICS671M-03IT
ICS671-03
3.3 Volt Zero Delay, Low Skew Buffer
MDS 671-03 A
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408) 295-9800 tel www.icst.com
2
Revision 072501
PRELIMINARY INFORMATION
Pin Descriptions
Key: I = Input; O = output; P = power supply connection. Outputs have a weak internal pull-down when in tri-state
mode.
Pin Assignment
External Components
The ICS671-03 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.01μF should be connected between VDD and GND on pins 4 and 5, and VDD and GND on pins 13 and 12, as
close to the device as possible. A series termination resistor of 33
may be used close to each clock output pin to
reduce reflections.
16
15
14
13
12
16 pin narrow (150 mil) SOIC
11
10
9
1
2
3
4
5
6
7
8
CLKA1
GND
FBIN
CLKIN
VDD
S2
CLKB1
CLKB2
VDD
GND
CLKB3
S1
CLKB4
CLKA4
CLKA3
CLKA2
Number
1
2, 3, 14, 15
4, 13
5, 12
6, 7, 10, 11
8
9
16
Name
CLKIN
CLKA1:A4
VDD
GND
CLKB1:B4
S2
S1
FBIN
Type
I
O
P
P
O
I
I
I
Description
Clock Input. (5 V tolerant)
Clock Outputs A1:A4. See above table. Outputs have weak pulldown resistors.
Power supply. Connect both pins to 3.3 V.
Connect to ground.
Clock Outputs B1:B4. See above table. Outputs have weak pulldown resistors.
Select input 2. See table above. Internal pull-up.
Select input 1. See table above. Internal pull-up.
Feedback Input. Connect to any output under normal operation. (5 V tolerant)
S2
0
0
1
1
S1
0
1
0
1
CLKA1:A4
Tri-state (Note 1)
Stopped Low
Running
Running
CLKB1:B4
Tri-state (Note 1)
Stopped Low
Running
Running
A & B Source
PLL
none
CLKIN (Note 2)
PLL
PLL Status
ON
OFF
OFF
ON
Output Clock Mode Select Table
Notes: 1. Outputs are in high impedance state with weak pulldowns.
2. Buffer mode only; not zero delay between input and output.
相關(guān)PDF資料
PDF描述
ICS671-06 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
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