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參數(shù)資料
| 型號(hào)： | ICS60101 |
| 英文描述： | LOW PHASE NOISE CLOCK MULTIPLIER |
| 中文描述： | 低相位噪聲時(shí)鐘乘法器 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 176K |
| 代理商： | ICS60101 |
L
OW
P
HASE
N
OISE
C
LOCK
M
ULTIPLIER
MDS 601-01 L
2
Revision 111204
Integrated Circuit Systems
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
ICS601-01
Pin Assignment
Multiplier Select Table
0 = connect directly to ground
1 = connect directly to VDD
Pin Descriptions
1
2
3
VDD
4
REFEN
5
6
GND
7
8
GND
REFOUT
S3
S1
GND
X2
S2
VDD
16
CLK
VDD
X1/ICLK
S0
OE
15
14
13
12
11
10
9
16 Pin (150 mil) TSSOP or SOIC
S3
S2
S1
S0
CLK (see note 2 on following page)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TEST
TEST
Input x1
Input x3
Input x4
Input x5
Input x6
Input x8
TEST
Crystal osc. pass through (no PLL)
Input x2
TEST
Input x8
Input x10
Input x12
Input x16
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
2
CLK
REFEN
Output
Input
Clock output from VCO. Output frequency equals the input frequency times multiplier.
Reference clock enable. Turns off the buffered crystal oscillator clock (stops low) when low.
3
VDD
Power
Connect to +3.3V or +5V. Must match other VDDs.
4
VDD
Power
Connect to +3.3V or +5V. Must match other VDDs.
5
VDD
Power
Connect to +3.3V or +5V. Must match other VDDs.
6
X2
XO
Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal.
Leave disconnected for an external clock input.
7
S1
Input
Multiplier select pin 1. Determines CLK output per table above. Internal pull-up.
8
X1/ICLK
XI
Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal or clock.
9
S2
Input
Multiplier select pin 2. Determines CLK output per table above. Internal pull-up.
10
S3
Input
Multiplier select pin 3. Determines CLK output per table above. Internal pull-up.
11
S0
Input
Multiplier select pin 0. Determines CLK output per table above. Internal pull-up.
12
OE
Input
Output Enable. Tri-states both output clocks when low. Internal pull-up.
13
REFOUT
Output
Buffered crystal oscillator clock output. Controlled by REFIN.
14 - 16
GND
Power
Connect to ground.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS601-01 | 制造商:ICS 制造商全稱:ICS 功能描述:Low Phase Noise Clock Multiplier |
| ICS601-02 | 制造商:ICS 制造商全稱:ICS 功能描述:Low Phase Noise Clock Multiplier |
| ICS601-21 | 制造商:ICS 制造商全稱:ICS 功能描述:LOW PHASE NOISE CLOCK MULTIPLIER |
| ICS601-25 | 制造商:ICS 制造商全稱:ICS 功能描述:LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER |
| ICS601G-01 | 功能描述:IC CLOCK MULTIPLIER 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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