參數(shù)資料
型號: ICS541M
英文描述: PRELIMINARY INFORMATION PLL Clock Divider
中文描述: 初步資料PLL時鐘分頻器
文件頁數(shù): 3/4頁
文件大?。?/td> 59K
代理商: ICS541M
ICS541
PLL Clock Divider
MDS 541 B
Integrated Circuit Systems, Inc. 525 Race Street San JoseCA 95126 (408)295-9800tel www.icst.com
3
Revision 082500 Printed 11/14/00
PRELIMINARY INFORMATION
Electrical Specifications
Parameter
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Inputs
Clock Output
Ambient Operating Temperature
Soldering Temperature
Storage temperature
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Operating Voltage, VDD
Input High Voltage, VIH, ICLK only, Note 1
Input Low Voltage, VIL, ICLK only, Note 1
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, CMOS level
IDD Operating Supply Current, 80 in, 40+20 out No Load, 5.0V
IDD Operating Supply Current, 40 in, 40+20 out No Load, 3.3V
Short Circuit Current
Input Capacitance, S1, S0, OE
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Input Frequency, clock input
Input Frequency, clock input
Skew of output clocks
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Conditions
Minimum
Typical
Maximum
Units
Referenced to GND
Referenced to GND
Referenced to GND
7
V
V
V
C
C
C
-0.5
-0.5
0
VDD+0.5
VDD+0.5
70
260
150
Max of 10 seconds
-65
3
5.5
V
V
V
V
V
V
V
V
ICLK (Pin 1)
ICLK (Pin 1)
S0, S1, OE
S0, S1, OE
IOH=-25mA
IOL=25mA
IOH=-4mA
(VDD/2)+1
(VDD/2)-1
2
0.8
2.4
0.4
VDD-0.4
15
8
±70
4
mA
mA
mA
pF
Each Output
Pins 4, 5, 6
at VDD = 5V
at VDD = 3.3V
rising edges at VDD/2
0.8 to 2.0V
2.0 to 0.8V
at VDD/2
4
4
156
135
500
55
MHz
MHz
ps
ns
ns
%
1
1
45
49 to 51
Note 1: CMOS level input; nominal trip point is VDD/2.
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