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參數(shù)資料
| 型號： | ICS527-01 |
| 英文描述： | Clock Slicer⑩ User Configurable Zero Delay Buffer |
| 中文描述： | ⑩時鐘切片機用戶可配置零延遲緩沖器 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 113K |
| 代理商： | ICS527-01 |
ICS527-01
Clock Slicer
User Configurable Zero Delay Buffer
MDS 527-01 B
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126(408)295-9800tel www.icst.com
4
Revision 020801
FB frequency = Input frequency (FDW+2)
(RDW+2)
Determining (setting) the ICS527-01 Dividers
The user has full control in setting the desired output clocks over the range shown in the table on page 2. The
user should connect the divider select input pins directly to ground (or VDD, although this is not required
because of internal pull-ups) during Printed Circuit Board layout, so that the ICS527-01 automatically
produces the correct clock when all components are soldered. It is also possible to connect the inputs to
parallel I/O ports to switch frequencies.
The dividers are expressed as integers. For example, if a 50 MHz output on CLK1 is desired from a
40 MHz input, the reference divider word (RDW) should be 2 and the feedback divider (FDW) should be
3 which gives the required 5/4 multiplication. If multiple choices of divider are available, then the lowest
numbers should be used. In this example, the output divide (OD) should be selected to be 2. Then R6:R0
is 0000010, F6:F0 is 0000011 and S1:S0 is 00. Also, this example assumes CLK1 is connected to FBIN.
You may also fax this page to MicroClock/ICS at 408 295-9818, or send an e-mail to ics-mk@icst.com.
Be sure to indicate the following:
Your Name ________________ Company Name___________________ Telephone_________________
Respond by e-mail (list your e-mail address) __________________or fax number ___________________
Desired input clock (in MHz) _______________ Desired output frequency________________
Also, the following operating ranges should be observed:
300 kHz < Input Frequency
(RDW+2)
Where Reference Divider Word (RDW) = 0 to 127
Feedback Divider Word (FDW) = 0 to 127
FB frequency is the same as either CLK1 or CLK2 depending on
feedback connection
The output of the ICS527-01 can be determined by the following simple equation:
The output divide should be selected depending on the frequency of CLK1.
The table on page 2 gives the ranges.
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| ICS527R-01 | Inductor; Inductor Type:Power; Inductance:100uH; Inductance Tolerance:+/- 25 %; Series:CTX; Package/Case:PCB Surface Mount; Core Material:Amorphous Metal; Current, lt rms Parallel:0.75A; Current, lt rms Series:0.38A RoHS Compliant: Yes |
| ICS527R-01I | Clock Slicer⑩ User Configurable Zero Delay Buffer |
| ICS527R-01IT | Clock Slicer⑩ User Configurable Zero Delay Buffer |
| ICS527R-01T | Inductor; Inductor Type:Power; Inductance:100uH; Inductance Tolerance:+/- 25 %; Series:CTX; Package/Case:PCB Surface Mount; Core Material:Amorphous Metal; Current, lt rms Parallel:1.05A; Current, lt rms Series:0.53A RoHS Compliant: Yes |
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| ICS527-03 | 制造商:ICS 制造商全稱:ICS 功能描述:Clock Slicer User Configurable PECL Output Zero Delay Buffer |
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| ICS527R-01 | 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS527R-01I | 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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